Clock latch circuit with reset and less time delay and chip

Abstract

The invention discloses a clock latch circuit with reset and less time delay and a chip. When the clock latch circuit is powered on and reset, a reset module is conducted to enable the clock latch circuit to be reset to a required state immediately, so time and current consumption caused by an uncertain output state of the circuit is avoided; when the clock latch circuit is powered on and reset, the reset module is closed, if the clock latch circuit is in a data transmission state, the transmission gate module is conducted, the data latch access is closed, and the output state of the clock latch circuit is equal to the input state, so the situation that the circuit has a large access due to conduction of a data latching access is avoided, the current consumption is reduced, and the switching speed of different states of the circuit is increased; if the clock latch circuit is in the data latch state, the transmission gate module is closed, the data latch path is connected, and the output state of the clock latch circuit is kept unchanged.

Description

technical field [0001] The invention relates to the technical fields of electronics and microelectronics, in particular to a clock latch circuit and chip with reset and less time delay. Background technique [0002] In IC circuits, it is often necessary to latch data, so a latch (latch) circuit is born. [0003] The traditional clock latch circuit generally adopts such as figure 1 The way shown is achieved: [0004] When CLK=1, CLK_N=0, OUT=IN (that is, the circuit is in the data transmission state); when CLK=0, CLK_N=1, OUT remains unchanged (that is, the circuit is in the data latch state). [0005] The above circuit has the following limitations: [0006] 1. When power-on reset, the state of out cannot be determined (when CLK=0, the state of out depends on the state of point b, because the state of point b may be 1 or 0 (depending on the state before the transmission gate is closed) The state of point b), resulting in the state of out cannot be determined); when CLK=1...

AI Technical Summary

Problems solved by technology

[0006] 1. When power-on reset, the state of out cannot be determined (when CLK=0, the state of out depends on the state of point b, because the state of point b may be 1 or 0 (depending on the state before the transmission gate is closed) The state of point b), resulting in the state of out cannot be determined); when CLK=1, when the states of IN and OUT are different, I0 and I2 will fight (that is, the states of point a and point b are not the same, if point b The state of point b is 1, and the state of point b is inverted and transmitted to OUT (ie OUT=0) output. If the state of point a is 0 at this time, because CLK=1, the state of point a will be transmitted to b through the transmission gate. point (that is, b=0), but at this time the state of OUT is reversed and it will return to point b (that is, b=1), which will lead to a fight), although because of the role of the transmission gate (because the input of the transmission gate There will be a difference in signal strength between the terminal and the output terminal. It is generally believed that the input signal of the transmission gate will be stronger than the output signal of the transmission gate) so that the states of point a and point b will eventually become the same, but it will take longer , consume excess current;

[0007] 2. After power-on reset, the moment CLK changes from 0 to 1 (that is, the circuit is in the data transmission state), when the states of IN and OUT are different, I0 and I2 will fight (same as the situation in point 1), so that Switching takes longer and consumes excess current, which also affects switching speed

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