FPGA-based AI chip neural network acceleration method

Abstract

The invention discloses an FPGA-based AI chip neural network acceleration method, which is characterized in that quantitative training is carried out when a YOLO network is trained, and a floating point algorithm of the neural network is converted into a fixed point algorithm, so that the occupation of a memory is greatly reduced, the calculation speed and bandwidth are improved, and the effect of reducing power consumption is achieved; an HLS development mode is adopted to quickly generate an accelerator IP core of the YOLO convolutional neural network based on a Darknet framework, and meanwhile, convolution calculation is transformed, so that the calculation magnitude is greatly reduced; and multiplying unit resources consumed by convolution calculation are greatly reduced, meanwhile, on the basis that high precision is guaranteed, the hardware resource utilization rate of the FPGA is greatly increased, and power consumption generated by calculation is greatly reduced.

Description

technical field [0001] The invention relates to the field of neural network acceleration, in particular to an FPGA-based AI chip neural network acceleration method. Background technique [0002] With the development of artificial intelligence, convolutional neural networks have been widely used in speech recognition, image recognition, image segmentation, and natural language processing. As a computationally intensive algorithm, it includes a large number of convolution operations, addition operations, nonlinear operations, and pooling operations, involving a large number of signal connections, making the neural network parameters too large, and the operation process requires a lot of Computing power, resulting in slow running speed. Therefore, optimizing the neural network model and selecting the appropriate CNN computing hardware can greatly increase the computing speed of the neural network and obtain the best performance of the algorithm and hardware. [0003] The exis...

AI Technical Summary

Problems solved by technology

[0005] The FPGA accelerator based on VGG network acceleration is specifically optimized for the characteristics of the VGG network. It achieves a computing power of up to 1 790 GOP / s on the Arria10GX1150 FPGA, but VGG network acceleration will consume more computing resources and use more parameters. , resulting in more memory usage, poor performance, and slow computation

And the accelerator can only support a single specific network acceleration, which cannot meet the needs of generalization

[0006] Designing a hardware accelerator based on GPU, although GPU has a natural advantage in parallel computing, it has great disadvantages in terms of cost and power consumption: the chip consumes a lot of power, and the too large size is difficult to apply to mobile platforms, and cannot meet some specific requirements. CNN Computing Requirements in Scenarios

The development cycle of a specific CNN accelerator based on RTL FPGA is very long; from researching deep learning algorithm, simulation-based functional design, optimizing synthesizable architecture, compiling integrated FPGA system to timing analysis and functional verification , the process is numerous and complex, and the development efficiency is low

[0008] ASIC-based design chips have the advantage of being customizable, but the hardware design and development cycle of ASIC accelerators is long, the cost is high, and the product's portability is low. After the hardware is generated, it usually cannot be changed, and the flexibility is not high.

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