Method for manufacturing semiconductor integrated circuit

Abstract

Isolation characteristics of an isolation trench can be enhanced. Elements to be isolated by an isolation trench (STI 2) are formed in active semiconductor regions shown by arrows 30 and 31 on a semiconductor substrate 1. The STI 2 is filled with SiOF.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, a semiconductor device, a method for manufacturing a semiconductor integrated circuit, and a method for manufacturing a semiconductor device, in particular to element separation used in a semiconductor integrated circuit or a semiconductor device, a sidewall spacer for a MOS transistor, and a method for connecting semiconductor devices. Interlayer insulation of wiring and wiring of integrated circuits. Background technique [0002] Figure 36 with Figure 37 It is a typical diagram showing an example of a conventional semiconductor integrated circuit having an element isolation region. Figure 36 A layout diagram of a semiconductor integrated circuit is shown in . Figure 37 showing along Figure 36 The structure of the profile of the A-A line. [0003] Figure 36 ~ Figure 37 The MOS transistor described in is, for example, a constituent element of a semiconductor memory cell. [...

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Problems solved by technology

Therefore, there is a problem that it is difficult to insert a slit in a wiring narrower than about 0.1 μm in width using the technique described in this publication.

[0026] Conventional isolation trenches of semiconductor integrated circuits are constructed as described above, and there is a problem that microscopic defects are generated on the inner walls of the trenches during etching and heat treatment due to etching damage and contact between materials with different volume expansion rates.

[0027] In addition, in the conventional manufacturing method of semiconductor integrated circuits, when the dielectric constant of the isolation trench is reduced by providing the cavity, there is a problem that the process of providing the cavity in the isolation trench is complicated and the production is difficult.

[0028] In addition, in the conventional semiconductor integrated circuits, there is a problem that the operating speed of the semiconductor integrated circuits is reduced due to the interlayer film provided between the wirings or between the wirings and the semiconductor substrate.

[0029] In the existing manufacturing method of semiconductor devices, the implantation of impurities for forming source / drain regions is performed after forming holes in the sidewall spacers, and the following problems exist in the process: Poor LDD structure with sufficient impurity concentration is difficult

In addition, in order to form a poor LDD structure having a sufficient impurity concentration, the void needs to be made small, so that there is a problem in that since the side wall spacer damaged by ion implantation remains on the source / drain region, the An interface energy level is generated at the interface between the sidewall spacer and the silicon substrate, and a part of the electrons flowing from the source through the drain region to the drain is trapped by the interface energy level, which becomes the main cause of scattering of the leakage current flowing near the interface, reduce leakage current

[0030] In addition, in the conventional semiconductor device and its manufacturing method, there is a problem that the mobility of carriers in the semiconductor substrate directly under the gate insulating film is lowered due to stress applied to the gate electrode, thereby deteriorating the current driving force drop

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