Circuit time sequence optimization method based on register flexible time sequence library

Abstract

The invention discloses a circuit time sequence optimization method based on a register flexible time sequence library, which comprises the following steps of: firstly, simulating a register under the conditions of multiple groups of input signal conversion time, clock signal conversion time and register load capacitance respectively, and obtaining corresponding actual propagation delay at the moment by changing establishment relaxation and keeping relaxation of the register; obtaining specific input signal conversion time, clock signal conversion time and register load capacitance through linear interpolation, and establishing and keeping actual propagation delay of the register under relaxation, so that a flexible time sequence library of the register is established; then, performing static time sequence analysis on all register paths in the circuit by utilizing the library, and finding a minimum clock period meeting the condition that the establishment time margin and the retention time margin are both greater than zero by changing the establishment relaxation and the retention relaxation of the register; therefore, the circuit performance is improved under the condition that the circuit design is not changed and the circuit area overhead is not increased.

Description

technical field [0001] The invention relates to a digital integrated circuit timing optimization method, which belongs to the technical field of EDA. Background technique [0002] Static timing analysis is an important step in verifying whether the circuit timing constraints are satisfied in digital integrated circuit circuits. When using the traditional register timing library for static timing analysis, the propagation delay of the register is considered to be related to the setup time (the minimum time for the input data to remain stable before the clock signal jumps) and the hold time (the minimum time for the input data to remain stable after the clock signal jumps). The shortest time to maintain stability) is irrelevant, and the three are uniquely determined by the input signal conversion time of the register, the clock signal conversion time and the register load capacitance. In practice, however, for a given input signal transition time, clock signal transition time...

AI Technical Summary

Problems solved by technology

If the minimum clock cycle (corresponding to the highest operating frequency) does not meet the design requirements, the circuit needs to be optimized, paying additional design iteration time and circuit area overhead

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