Test method of semiconductor structure and test sample

Abstract

The embodiment of the invention discloses a test method of a semiconductor structure and a test sample. The method comprises the following steps that: a semiconductor structure is provided, wherein the semiconductor structure comprises a plurality of insulating layers, a plurality of sacrificial layers, and a plurality of packed columns, wherein the plurality of insulating layers and the plurality of sacrificial layers are alternately stacked, and the plurality of packed columns penetrate through the semiconductor structure and are distributed in an array; the semiconductor structure is cut to form a to-be-tested sample, wherein the to-be-tested sample comprises a first surface and a second surface which are oppositely arranged, and an included angle between the first surface or the second surface and the axial direction of the packed columns is a first acute angle; the sacrificial layers from the first layer to the Nth layer and the plurality of packed columns are exposed on the first surface or the second surface, wherein N is a natural number; scanning detection is executed on the to-be-detected sample to obtain a plurality of scanning patterns of the packed columns; fitting processing is carried out on the scanning patterns to obtain a plurality of fitting patterns of the packed columns; and deformation directions of the plurality of packed columns are determined based on the scanning patterns and the fitting patterns.

Description

technical field [0001] Embodiments of the present disclosure relate to the field of semiconductor device testing, and in particular, to a testing method and a testing sample of a semiconductor structure. Background technique [0002] In order to improve the integration and bit density of the memory, a stacked structure can be formed on the substrate, which includes insulating layers and sacrificial layers alternately stacked along a direction perpendicular to the plane of the substrate, and channel holes penetrating the stacked structure. Due to the different composition materials of the insulating layer (for example, silicon oxide) and the sacrificial layer (for example, silicon nitride), it is easy to cause damage to the sacrificial layer in the process of etching and forming the channel hole, so that the formed channel hole side The irregular shape of the walls reduces the electrical performance and reliability of the memory. [0003] In the related art, electron microsc...

AI Technical Summary

Problems solved by technology

However, the way of preparing test samples by this method is complicated, and the information obtained is less, so it is difficult to fully reflect the damage of the sacrificial layer

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