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Power-on reset circuit structure

A circuit structure and electric reset technology, applied in data reset devices, electrical components, electronic switches, etc., can solve the problem of high power consumption

Pending Publication Date: 2021-12-17
UNIV OF ELECTRONIC SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the power consumption of this power-on reset circuit is relatively high

Method used

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  • Power-on reset circuit structure
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  • Power-on reset circuit structure

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Experimental program
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Embodiment Construction

[0017] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0018] Such as figure 1 As shown, it is a schematic diagram of the overall structure of the power-on reset circuit structure of the present invention, including a start-up circuit module, a delay unit module and a debounce circuit module;

[0019] Such as figure 2 Shown is a schematic structural diagram of the starting circuit module of the present invention. The starting circuit module signals include feedback input signal A1, external connections A2 (VDD), A3 (GND), internal node signals A4, D, output signal Y, and the output signal is used as the first power-on reset signal. The first part is on the left, above are 5 PMOS tubes connected in series, below are 7 NMOS tubes connected in series, these MOS tubes all use the MOS tube of special size, what use in the concrete implementation of the present invention is the inverting ratio tube, like this and the follow...

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PUM

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Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a power-on reset circuit structure. In the field of integrated circuit design, various integrated circuits may include a power on reset (POR) circuit. Generally, when an integrated circuit is powered on, the voltage and logic states of many electronic components and circuit nodes are unstable when the supply voltage has not reached a stable expected state. In order to enable an integrated circuit system to start to operate from a state expected by a designer after being powered on each time, a POR circuit needs to be utilized to generate a reset signal when a power supply is powered on, and the IC system is forced to be in an initial state expected by the designer, so that an unstable state at the beginning of power-on is eliminated. The power-on reset circuit structure comprises a starting module, a time-delay circuit module and a de-jittering circuit module. Reliable reset signals are guaranteed under the conditions of slow power-on and fast power-on, and power-on reset of an integrated circuit system is achieved.

Description

technical field [0001] The invention belongs to the field of integrated circuits, and in particular relates to a power-on reset circuit structure. Background technique [0002] In the field of integrated circuit design, various integrated circuits may include a power on reset (POR: Power On Reset) circuit. Usually, when the integrated circuit is powered on, the voltage and logic state of many electronic components and circuit nodes are unstable when the power supply voltage has not reached the expected stable state. In order to make the integrated circuit system start to operate from the state expected by the designer every time it is powered on, it is necessary to use the power-on reset circuit to generate a reset signal when the power is turned on, forcing the IC system to be in the initial state expected by the designer. , thereby eliminating the unstable state at the initial power-up. [0003] The commonly used power-on reset circuit consists of a capacitor-resistor st...

Claims

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Application Information

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IPC IPC(8): H03K17/22G06F1/24
CPCH03K17/223G06F1/24Y02D10/00
Inventor 李建军黄双杜涛
Owner UNIV OF ELECTRONIC SCI & TECH OF CHINA