Negative capacitance junction-free nanowire field effect transistor and manufacturing method thereof

Abstract

The invention discloses a negative capacitance junction-free nanowire field effect transistor and a manufacturing method thereof. The transistor comprises a junction-free nanowire (10), the outer surface of a source region (12) is covered with an active electrode layer (32), and an active dielectric layer (22) is arranged between the source electrode layer (32) and part of the surface of the source region (12); the outer surface of the drain region (13) is covered with a drain electrode layer (33), and a leakage dielectric layer (23) is arranged between the drain electrode layer (33) and part of the surface of the drain region (13); the peripheral surface of the annular channel region (11) is sequentially covered with a gate dielectric layer (21), a ferroelectric material layer (50) and a gate electrode layer (31). Due to the negative capacitance characteristic of the junction-free transistor based on the ferroelectric material, when the device works in an accumulation region, the driving current of the device is larger, and the starting speed of the device is increased; when the device works in a depletion region, the subthreshold slope and the leakage current of the device are reduced, the power consumption of the device is reduced, and the electrical performance of the device is greatly improved.

Description

Technical field [0001] The present invention relates to the field of semiconductor integrated circuit applications, and more particularly to a negative capacitively free knotted nanowire field effect transistor and a manufacturing method thereof. Background technique [0002] The MOS device follows "Moore Law", and the feature size is continuously proportional to micro-shrinkage, and the MOS field effect transistor device based on PN junction is increasingly obvious: for example, in order to reduce the device size, the source drain distance of the device is constantly shortened, resulting in source leakage Direction, generate short channel effects, so that the gate control of the device is deteriorated, the device performance and reliability are severely degraded; the method of making super steep pn junctions is proposed in the prior art from preventing the source leakage to avoid short channel effects, but Since the doped atom is difficult to have a statistical distribution and ...

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Problems solved by technology

[0006] However, when the junction-free device of the charge-plasma structure in the prior art is applied, the on-state current is small, the opening speed is relatively slow, and the power consumption is high. Therefore, the junction-free device of the charge-plasma structure in the prior art Electrical performance needs to be improved

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