Universal JTAG (Joint Test Action Group) debugging method and system with extensible interface

Abstract

The invention provides a universal JTAG (Joint Test Action Group) debugging method and a universal JTAG debugging system with an extensible interface. The universal JTAG debugging method comprises the following steps: packaging a JTAG host controller into IP (Internet Protocol) equipment of a peripheral bus port; hardware resources in the development board are called, the JTAG host IP is hooked to a hardware system, and the minimum hardware field programmable gate array design of the debugging system is completed; according to the characteristics of the development board, completing the boot loader transplantation work; compiling is carried out in the transplanted boot loader, and the binary file is solidified to the development board; the debugging device is connected with the upper computer, the debugging device is connected with the target debugging chip, the upper computer runs the hyperterminal software, and the debugging work of the target chip is completed through the data JTAG debugging instruction. The system can be flexibly integrated into an embedded system with a processor core, an RAM (Random Access Memory), an ROM (Read Only Memory), a GPIO (General Purpose Input / Output) pin, a JTAGMASTER and a UART (Universal Asynchronous Receiver / Transmitter) device, the establishment of a hardware part of a debugging system is completed, and the flexibility is realized. the module JTAGMaster controller can realize JTAG protocol conversion and can be connected with multiple paths of JTAG equipment with the same or different characteristics at the same time.

Description

technical field [0001] The invention relates to the technical field of electronic equipment maintenance, in particular to a universal JTAG debugging method and system with expandable interfaces. Background technique [0002] The integrated circuit industry develops in accordance with the law of Moore's law. The scale of integrated circuits is getting larger and larger, and the circuits that can be integrated on a single chip are becoming more and more complex. It means that in the chip development stage, it is easier to face risk events such as unknown failure conditions, material defects, and manufacturing deviations, which will lead to situations where the chips returned from the tape-out cannot work normally as expected or the performance is not optimal. Therefore, in 1990, the IEEE 1149.1 standard was released based on the testability design considerations of the chip. At present, the ARM processor series, PowerPC processor series, and complex control devices such as PC...

AI Technical Summary

Problems solved by technology

However, this invention does not have a module JTAG Master controller, and cannot realize JTAG protocol conversion and simultaneous connection of multiple JTAG devices with the same or different characteristics, and the scalability is not enough

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