High-speed burst mode clock data recovery circuit suitable for PAM4 signal

Abstract

The invention discloses a high-speed burst mode clock data recovery circuit suitable for PAM4 signals. The high-speed burst mode clock data recovery circuit comprises a sampling decision circuit, a phase discrimination circuit, a majority voting circuit, an oversampling logic unit, a digital phase control module, a digital loop filter, an orthogonal clock generation circuit and a phase synthesis module. And the oversampling logic unit is used for controlling the switching of the loop locking mode between an oversampling mode and a phase discrimination locking mode, carrying out oversampling on a PAM4 data signal quantization result and outputting a control signal. Due to the fact that the oversampling locking loop is additionally arranged, the initial coding sequence is rapidly sampled, the approximate clock phase is determined, the locking mechanism with the small bandwidth is achieved in cooperation with the binary phase discriminator locking loop, and low-jitter receiving is achieved. According to the invention, the sampling unit in the oversampling mode multiplexes a sampler originally used for edge sampling and a partial sampler for PAM4 decoding, an additional sampling circuit is not needed, and the system power consumption is reduced while rapid locking of a loop is realized.

Description

technical field [0001] The invention belongs to the fields of optical communication and integrated circuits, and more specifically relates to a high-speed burst mode clock data recovery circuit suitable for PAM4 signals. Background technique [0002] A clock and data recovery circuit (CDR for short) plays a vital role in a serial communication system. In a high-speed serial communication system, only serial data is transmitted on the channel, and no clock signal is transmitted, and the data receiving end receives the data signal and performs clock recovery. The function of the clock data recovery circuit is to extract the clock from the data signal according to the reference clock, and then use the recovered clock to retime the received data to obtain a data reception result that meets the specification. [0003] The use of the PAM4 signal increases the data rate, and the receiver performs simultaneous phase detection on the decoded three-way data signals, which improves th...

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Problems solved by technology

[0005] Aiming at the defects of the prior art, the purpose of the present invention is to provide a high-speed burst mode clock data recovery circuit and receiver suitable for PAM4 signals, aiming to solve the complex circuit caused by the introduction of the ADC in the oversampling mode in the prior art. The problem of a large increase in speed and power consumption

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