Circuit for configuring, reading back and refreshing SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) and operation method

Abstract

The invention discloses a circuit for configuring, reading back and refreshing an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array). The circuit comprises a storage controller, a serial port module, a data path, an FPGA interface module, a state machine and a configuration register, the storage controller reads data in the memory and sends the data to the serial port module or the FPGA interface module through a data path; the serial port module is in two-way communication connection with the upper computer; the FPGA interface module receives data in the memory or data of the serial port module through a data path, and configures, reads back and refreshes the FPGA; the circuit disclosed by the invention can be used for detecting and updating code matching errors in an SRAM type FPGA (Field Programmable Gate Array) chip, and the adaptability of the FPGA to a severe environment is enhanced. And the circuit adopts the serial port module to receive information of an upper computer, so that the circuit can work according to a default predetermined flow after being powered on, and the working state of the circuit can be monitored through the serial port module to set and adjust the working mode.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a circuit and an operation method for configuring, reading back and refreshing an SRAM FPGA. Background technique [0002] FPGA is Field Programmable Gate Array, which is a general-purpose integrated circuit paralleled with CPU and DSP. The FPGA chip includes resources such as sequential logic, combinational logic, wiring resources, memory array, operational logic array, clock network, IO logic, etc. Users can design the FPGA through graphical design or hardware description language (HDL) design input. On-chip resources are called, and then various digital circuits are built. [0003] After the user completes the FPGA function development and design, the circuit design needs to be converted into a binary code stream. The code stream only contains 0 and 1 digital combinations. The different digital combinations determine the circuit structure in the FPGA chip. Since ...

AI Technical Summary

Problems solved by technology

However, SRAM-type FPGAs have a disadvantage: when FPGAs are used in harsh environments such as irradiation environments and artificial satellites, the SRAM storage cells in the Configuration SRAM array are susceptible to charged particles, false flips, 0, 1 data An error occurs, which in turn causes the user circuit function of the FPGA to malfunction

This method can realize the configuration and readback of the FPGA, but the disadvantage is that the configuration information will be lost when the power is turned off. It is only suitable for debugging and cannot be used for on-site deployment of products and equipment.

Another method is: use the PROM to load the configuration when the FPGA is powered on. The advantage is that the PROM can store the configuration data in a non-volatile manner, and since the upper computer is not required in the working state, it can be deployed in the actual product. However, its disadvantage is that it can only load the configuration of the power-on configuration to the FPGA, and cannot read back, compare, and refresh the FPGA configuration.

[0007] After retrieval, Chinese Patent Publication No. CN202011191407.9 discloses a dynamic refresh method and device for SRAM-type FPGA configuration data. This patent has the following defects: it only supports SPI NOR Flash, has a single fixed function, and cannot adjust and set the working mode of the chip in real time.

Chinese Patent Publication No. CN202011420884.8 discloses an IP core for on-board SRAM FPGA configuration and refresh control. This patent has the following defects: it only supports parallel port NOR Flash, the function is fixed and single, and the working mode of the chip cannot be adjusted in real time. set up

[0009] (1) The configuration of SRAM-type FPGA SRAM array is susceptible to the influence of space particles, cosmic rays, and charged particles, and then false flips occur

[0010] (2) The JTAG configuration method cannot carry out the actual deployment of the product on site

[0011] (2) The PROM mode cannot be read back and refreshed

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