Peak holding circuit with peak mark output
A technology of peak hold circuit and peak detection circuit, which is applied in the direction of electrical components, pulse processing, pulse technology, etc., can solve the problems of not being able to output peak signal, only outputting peak signal, limiting precision and stability, etc., to avoid precision Reduce, improve detection accuracy and energy resolution, and improve the effect of carrying capacity
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[0028] Such as figure 2 , Figure 9 Shown, including peak hold circuit, peak detection circuit, peak marker output buffer. Among them, the output of the peak hold circuit comes from the output of the previous stage, which can be the output of the filter shaper or the radiation signal output by other detection circuits. The two output terminals of the peak hold circuit are the peak output and the current mirror voltage signal respectively. The current mirror voltage signal is connected to the input terminal of the peak detection circuit, and the output terminal of the peak detection circuit is connected to the peak marker output buffer to output the peak marker signal to other modules.
[0029] Such as image 3 As shown, the peak hold circuit includes 4 PMOS transistors, respectively MP1, MP2, MP3, MP4, three NMOS transistors, respectively MN1, MN2, MN3, a holding capacitor CH, two transmission gates T1, T2, where T1 and T2 are controlled by external RESET signal and HOLD s...
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