Method for solving chip timing sequence deterioration caused by metal filling Metal Fill

Abstract

The embodiment of the invention relates to a method for solving chip timing sequence deterioration caused by metal filling Meta < l > F l. In the step of layout and wiring, the establishment time and the retention time of each time sequence endpoint on each time sequence path in a chip are obtained; determining a first violation time corresponding to the establishment time violation and a second violation time corresponding to the retention time violation of each time sequence endpoint according to the clock period of the chip; determining whether a time interval between the establishment time of each time sequence endpoint and the first violation time meets a set time sequence margin or not for each time sequence path, and determining whether a time interval between the termination time after the retention time from the establishment time and the second violation time meets the set time sequence margin or not for each time sequence path; and when any one of the time sequence path and the time sequence path is not satisfied, determining the time sequence path as a time sequence risk path, generating a virtual barrier layer according to a set width, and setting the virtual barrier layer along the time sequence risk path so as to block the execution of metal filling at the position occupied by the virtual barrier layer during subsequent metal filling.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a method for solving the deterioration of chip timing caused by metal filling. Background technique [0002] Chemical-mechanical polishing (CMP) is a step in a semiconductor process. However, in the process of wafer processing, this process step will cause a large concave area in the area without interconnecting metal lines, so that after the CMP process, the isolation layer between the metal lines and the metal lines will be uneven. This problem can cause signal delays to the chip. [0003] In order to cope with this situation, an electronic design automation (Electronic Design Automation, EDA) tool of an integrated circuit provides a function of automatic insertion and filling of Metal Fill, which is already a very common application in the back-end design of integrated circuits. [0004] However, since the Metal Fill work is completed at the end of the entire design cycl...

AI Technical Summary

Problems solved by technology

They can cause timing degradation in the final real chip with serious consequences

[0006] For this reason, chip design engineers have to re-analyze on the basis of adding these new metal patterns to the entire chip (that is, after filling the Metal Fill), including re-doing a complete parasitic parameter extraction, and then bringing in these new Complete physical verification, timing verification, and functional verification of the increased parasitic parameters, and if new problems caused by filling Metal Fill are found in the process, the design needs to be changed again, which will inevitably affect the entire design cycle

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