Surrounding gate transistor and preparation method thereof

Abstract

The invention relates to a gate-all-around transistor and a preparation method thereof. A gate medium is formed by adopting the following method: firstly forming a first high-k dielectric layer, and then removing the first high-k dielectric layer in a partial region; forming a second high-k dielectric layer; wherein the first high-k dielectric layer and the second high-k dielectric layer have different electronegativity or different atomic radiuses. Different device thresholds are formed by using different structures of the two high-k dielectric layers in different regions, and better selectivity is provided for multi-threshold integration of the device.

Description

technical field [0001] The present invention relates to the field of fabrication technology of a surrounding gate transistor, in particular to a surrounding gate transistor and a preparation method thereof. Background technique [0002] Integrated circuit feature sizes continue to shrink, and traditional tri-gate or dual-gate FinFETs are limited at sub-3nm nodes. This is because with the further reduction of the spacing between the gate lines of the FinFET, the problem of the electrostatic integrity of the channel of the fin transistor is rapidly exacerbated, which directly restricts the further improvement of transistor performance and integration. The electrostatic integrity problem mentioned here refers to a series of gate control failures caused by the three-dimensional fin (Fin) channel structure of the fin transistor itself under the extremely short gate length, which is difficult to switch normally and leads to channel leakage. Issues related to increasing device and...

AI Technical Summary

Problems solved by technology

The GAA-FET fabricated by the above method has the following Figure 10 In the cross-sectional structure shown, in order to limit the channel height of the entire stacked nanosheets and improve the overall channel performance under the projection plane, the spacing between silicon nanosheets (the dotted circle in the figure) is extremely small, and there will be extremely complex It is difficult to fill or fill unevenly, which makes it difficult to precisely control the threshold of the device

On this basis, it will be a great challenge to achieve multi-threshold integration by using the traditional method of controlling the metal gate work function layer or other film thickness changes.

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