Convolutional neural network acceleration method with low off-chip transmission bandwidth requirement

Abstract

The invention relates to a convolutional neural network acceleration method with a low off-chip transmission bandwidth requirement, and belongs to the technical field of transmission. By performing reusability analysis on a data stream based on a'slice 'scheduling strategy and designing an independent scheduling strategy for each convolutional layer of a convolutional neural network model under the constraint of resources such as FPGA on-chip calculation, storage and logic, the pressure of high throughput on transmission is reduced, limited bandwidth is prevented from becoming the bottleneck of the overall performance of the system, and the performance of the system is improved. Therefore, the problem of memory access congestion in practical application is solved, the adaptation of deployment of the convolutional neural network model on an FPGA platform is improved, and the application scene of the convolutional neural network model is widened. The invention has the advantages of low cost, high integration level, low hardware resource consumption, simple structure, high reliability, easiness in implementation and the like, can effectively reduce the pressure of high throughput on transmission, and prevents limited bandwidth from becoming the bottleneck of the overall performance of the system, thereby solving the problem of memory access congestion in practical application.

Description

technical field [0001] The invention belongs to the technical field of transmission, and relates to a convolutional neural network acceleration method with low demand for off-chip transmission bandwidth. Background technique [0002] As a branch of deep learning, convolutional neural networks have been widely used in various scenarios due to their excellent accuracy, such as image processing, speech processing, etc. With the improvement of the accuracy of convolutional neural networks, today's top convolutional neural network models need to build a fairly deep convolutional layer structure to convert input image data into highly abstract representations, such as figure 1 shown. The increasing depth of neural networks poses new computational challenges, and the use of very deep neural networks is accompanied by a large number of multiply-accumulate (MAC) operations, which are not suitable for the architecture of general-purpose CPUs. The simple way to solve this problem is ...

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