Fan-out packaging structure and fan-out packaging method

Abstract

The invention provides a fan-out type packaging structure and a fan-out type packaging method, and relates to the technical field of semiconductors. The structure comprises a packaging element, a plastic packaging body, a first dielectric layer and a second dielectric layer, the packaging element is provided with a first bonding pad and a second bonding pad, the first bonding pad is lower than the second bonding pad, the plastic packaging body packages the packaging element in a plastic mode, the end face of the first bonding pad is exposed out of the surface of the plastic packaging body, and the end face of the second bonding pad is exposed out of the surface of the plastic packaging body. A first wiring layer is arranged on one side, far away from the packaging element, of the first bonding pad, and a first welding ball is arranged on the first wiring layer; the first dielectric layer is arranged on the side, away from the packaging element, of the first wiring layer, the end face of the second bonding pad is exposed out of the surface of the first dielectric layer, a second wiring layer is arranged on the side, away from the packaging element, of the second bonding pad, and second welding balls are arranged on the second wiring layer; a second dielectric layer is arranged on the side, away from the first wiring layer, of the second wiring layer. The structure can reduce the number of wiring layers and does not need to additionally increase conductive columns.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a fan-out packaging structure and a fan-out packaging method. Background technique [0002] In the existing fan-out process, it is usually necessary to arrange multiple layers of rewiring layers to connect the functional pads and ground pads on the chip to the outside. However, connecting the ground pads or functional pads to the outside requires conductive vias. , The conductive pillar connects the multi-layer rewiring layer to realize the fan-out expansion of the chip pad. When the number of rewiring layers produced is more, the required wiring layer process is more complicated, and the number of conductive holes will be more, resulting in an increase in cost. In addition, the conductive holes on the rewiring layer will inevitably increase the parasitic effect and capacitive effect between the wiring layers, which will cause signal transmission to be interfered ...

AI Technical Summary

Problems solved by technology

When the number of rewiring layers produced is more, the required wiring layer process is more complicated, and the number of conductive holes will be more, resulting in an increase in cost

In addition, the conductive holes on the rewiring layer will inevitably increase the parasitic effect and capacitance effect between the wiring layers, which will cause signal transmission to be interfered and the heat dissipation effect of the product will be poor.

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