Simulation method of simulation circuit of packaging box and test method of packaged chip

Abstract

The invention relates to a simulation method of a simulation circuit of a packaging box and a test method of a packaged chip, which are applied to the technical field of semiconductor microelectronic production, and the method comprises the following steps: establishing a simulation model of the packaging box; performing port excitation on the simulation model to generate an S parameter; a simulation circuit of the simulation model is obtained based on the S parameter, and the simulation circuit comprises a plurality of electromagnetic parasitic elements. The packaging box has the effect of reducing the influence of electromagnetic parasitic parameters in the packaging box on the packaged chip when the packaged chip is designed.

Description

technical field [0001] The present application relates to the technical field of semiconductor microelectronics production, and in particular, to a simulation method of a package box simulation circuit and a test method of a packaged chip. Background technique [0002] The production process of the packaged chip includes steps such as gluing, photolithography, metallization, peeling, probe testing, dicing, packaging, and packaging testing on the wafer. Among them, the probe testing is performed through a network with a probe head. The analyzer tests the electrical properties of the chips on the wafer, and the wafers that pass the probe test results are then processed into packaged chips after dicing and packaging. [0003] In the packaging step, the packaging box is the carrier of the wafer, and the wafer after passing the probe test needs to be packaged in the packaging box. When the wafer is packaged, the electromagnetic parasitic parameters will be introduced into the pac...

AI Technical Summary

Problems solved by technology

[0003] In the packaging step, the packaging box is the carrier of the wafer. It is necessary to package the wafer that has passed the probe test in the packaging box. When the wafer is packaged, electromagnetic parasitic parameters will be introduced into the packaging box. Electromagnetic parasitic parameters It will cause changes in the passband width, center frequency and passband square coefficient of the wafer, which will eventually lead to unqualified electrical performance of the packaged chip.

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