Method for improving metal gate contact hole etching process window

Abstract

The invention provides a method for improving a metal gate contact hole etching process window, and the method comprises the steps: providing a substrate, forming a plurality of device regions on the substrate, forming a metal gate in each device region, forming an interlayer dielectric layer on the substrate, and then grinding the interlayer dielectric layer to enable the metal gate to be exposed; forming a diffusion barrier layer on the interlayer dielectric layer and the metal gate; forming an etching barrier layer and an isolation layer which are stacked from bottom to top on the diffusion barrier layer; a photoresist layer is formed on the isolation layer, and the photoresist layer is opened through photoetching, so that the area, except the metal gate, on the at least one device area is exposed; removing the exposed isolation layer and the etching barrier layer and the diffusion barrier layer below the isolation layer; removing the photoresist layer, and then continuously forming an interlayer dielectric layer on the substrate; and etching the interlayer dielectric layer to form contact holes which are respectively communicated with the source region, the drain region and the metal gate. According to the method, matching process conditions such as interlayer dielectric layer and contact hole etching are not changed, the process window of through hole etching is improved, and the product reliability is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a method for improving the etching process window of a metal gate contact hole. Background technique [0002] 28nm high-voltage high-K metal gate process platform, such as figure 1 As shown, there are three operating voltage regions in the chip: low-voltage region (0.9V), medium-voltage region (8V) and high-voltage region (32V); the high-voltage region (32V device) has a larger metal gate (MG), After the aluminum chemical-mechanical planarization process, the metal gate in the high-voltage region wears more seriously than the low-voltage region and the medium-voltage region. Therefore, during the subsequent contact hole etching, the contact hole etching in the low-voltage region and the medium-voltage region stops above the metal gate. However, due to the small wear thickness of the metal gate in the high-voltage region, there is a risk of being etched and etched ...

AI Technical Summary

Problems solved by technology

[0002] 28nm high-voltage high-K metal gate process platform, such as figure 1 As shown, there are three working voltage areas in the chip: low voltage area (0.9V), medium voltage area (8V) and high voltage area (32V); among them, there is a larger metal gate (MG) in the high voltage area (32V device), After the aluminum chemical mechanical planarization process, the wear of the metal gate in the high-voltage area is more serious than that in the low-voltage area and the medium-voltage area. Therefore, during the subsequent contact hole etching, the contact hole etching in the low-voltage area and the medium-voltage area stops above the metal grid. However, the metal grid in the high-voltage area has the risk of being etched through the contact hole due to the small wear thickness, which has serious side effects on the performance of the product, such as reduced rated voltage and reduced reliability.

[0003] Therefore, there is a need for a method to improve the etching process window of the metal gate contact hole, so as to reduce the risk of the metal gate in the high voltage area being etched through the contact hole due to the small wear thickness

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