Test structure and monitoring method for floating source contact etching process
A test structure, source contact technology, applied in semiconductor/solid-state device testing/measurement, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as low efficiency, high cost, inability to real-time monitoring, etc., to achieve stable process , the effect of reducing the occupied space and saving the cost of slicing
Pending Publication Date: 2022-07-01
CSMC TECH FAB2 CO LTD
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- Description
- Claims
- Application Information
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Problems solved by technology
Disadvantages of existing technology: high cost, low efficiency, unable to monitor in real time
Method used
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[0042] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, some technical features known in the art have not been described in order to avoid confusion with the present application.
[0043] It should be understood that the application may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.
[0044] It will be understood that when an e...
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Abstract
The invention discloses a test structure and a monitoring method for a floating source contact etching process. The test structure comprises a semiconductor substrate which is configured as a lower pole plate and comprises an active region and a non-active region; the barrier layer is located on the active region of the semiconductor substrate; the dielectric layer covers the semiconductor substrate and the barrier layer; the upper electrode plates are arranged at intervals, the upper electrode plates are located above the active region, each upper electrode plate comprises a hole groove and a conductive material filled in the hole groove, and the hole grooves penetrate through the dielectric layer and extend to the barrier layer; the contact hole penetrates through the dielectric layer and extends to the semiconductor substrate; the upper polar plate metal interconnection is positioned above the plurality of upper polar plates and is electrically connected with the plurality of upper polar plates, and the plurality of upper polar plates are electrically connected to the upper polar plate bonding pad after being connected in parallel; and the lower polar plate metal interconnection is positioned above the contact hole and is electrically connected with the contact hole, and the semiconductor substrate is electrically connected to the lower polar plate bonding pad.
Description
technical field [0001] The present application relates to the field of semiconductors, and in particular, to a test structure and a monitoring method for a floating source contact etching process. Background technique [0002] At present, the device architecture of NLDMOS in the medium voltage range (16-80V) in the industry usually uses a metal plate, a floating source contact (floating source contact), or a gate plate. By enhancing and reducing the surface electric field (Reduce surface field, RESUF) in other ways, the off-state voltage (BVoff) can be improved under the same Rsp capability. [0003] Among them, the bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor process (BCD) floating metal (floating metal) is integrated in the through hole etching process to achieve together (no need for an additional layer of lithography to define floating metal) Metal, the technology is named as floating source contact (floating source contact),...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L23/544H01L21/66
CPCH01L22/32H01L22/12H01L22/14H01L22/26H01L23/544H01L22/00H01L29/78H01L29/66477
Inventor 金宏峰孙贵鹏林峰李春旭陈淑娴黄宇曹瑞彬赵伟
Owner CSMC TECH FAB2 CO LTD