Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure provided by the invention comprises the following steps: providing a substrate; a base pattern is formed on the substrate, the base pattern comprises a plurality of bit lines arranged in parallel, and isolation structures are arranged among the bit lines; forming a plurality of semiconductor columns arranged along the direction of the bit line on the surface of the bit line, wherein the bit line is electrically connected with the semiconductor columns; a surrounding gate structure is formed on the surface of the semiconductor column, the surrounding gate structure comprises a first insulating layer, a gate structure layer and a second insulating layer which are sequentially arranged on the side face of the semiconductor column, and the gate structure layer is electrically connected with the semiconductor column; and forming a first wire, a magnetic tunnel junction and a second wire which are stacked in sequence on the surface of the surrounding gate structure, wherein the first wire is electrically connected with the semiconductor column. The performance of the semiconductor structure is greatly improved, and the requirement for miniaturization is met.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor structure and a preparation method thereof. Background technique [0002] The need for inexpensive semiconductor structures with high performance drives integration density, which in turn places higher demands on semiconductor fabrication processes. [0003] The integration density of a two-dimensional (2D) or planar semiconductor structure is determined in part by the area occupied by the individual elements (eg, memory cells) that make up the integrated circuit. The area occupied by the individual elements is largely determined by the dimensional parameters (eg, width, length, pitch, narrowness, adjacent spacing, etc.) used to define the patterning techniques for the individual elements and their interconnections. Providing increasingly "fine" patterns requires the development and use of very expensive patterning equipment. [0004] As the semicondu...

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and providing increasingly "finer" patterns required the development and use of very expensive patterning equipment

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