Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for forming alignment mark in semiconductor process

An alignment mark, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc. Signal attenuation and other issues to achieve the effect of improving process reliability

Pending Publication Date: 2022-07-29
GALAXYCORE SHANGHAI
View PDF0 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for CIS (CMOS Image Sensor) or other processes that require epitaxy before the formation of the active region, after the epitaxy is completed, the shallow alignment marks will be affected by the planarization process, resulting in attenuation or disappearance of the alignment signal
[0003] In order to solve the alignment problem in the epitaxial semiconductor process before the active region is formed, a shallow trench can be formed in the alignment region and filled with a dielectric layer as an alignment mark, and then a deep trench can be formed in the device region and epitaxial, and then The active region is formed in the epitaxial layer. Although the alignment mark will not be affected by the planarization process after epitaxy, the disadvantage of this solution is that it increases the step of shallow trench photolithography and nested alignment. error

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for forming alignment mark in semiconductor process
  • Method for forming alignment mark in semiconductor process
  • Method for forming alignment mark in semiconductor process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] Figure 2-Figure 5 A preferred embodiment of the method for forming alignment marks in the semiconductor process of the present invention is shown.

[0025] like figure 2 As shown, a semiconductor substrate 100 is provided, a device region 100A and an alignment region 100B are defined (separated by dotted lines), and trenches 102 are simultaneously etched in the device region 100A and the alignment region 100B using a hard mask 101 . Preferably, the material of the hard mask 101 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0026] like image 3 , Figure 4 As shown, the first epitaxial layer 103 is formed in the trenches 102 of the device region 100A and the alignment region 100B, respectively, and the first epitaxial layer 103 and the hard mask 101 are sequentially planarized by chemical mechanical polishing. the surface of the substrate 100 .

[0027] Preferably, the width WB of the trench 102 in the alignmen...

Embodiment 2

[0033] Figure 6-Figure 9 Another preferred embodiment of the method for forming alignment marks in the semiconductor process of the present invention is shown.

[0034] like Image 6 As shown, a semiconductor substrate 200 is provided, a device region 200A and an alignment region 200B are defined (separated by dotted lines), and trenches 202 are simultaneously etched in the device region 200A and the alignment region 200B using a hard mask 201 , respectively. Preferably, the material of the hard mask 201 includes at least one or a combination of silicon oxide, silicon oxynitride, and silicon nitride.

[0035] like Figure 7 , Figure 8 As shown, a dielectric layer 206 and a polysilicon layer 207 are sequentially formed in the trenches 202 of the device region 200A and the alignment region 200B, respectively, and the polysilicon layer 207 and the hard mask 201 are sequentially planarized by chemical mechanical polishing, stopping at The surface of the semiconductor substra...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
widthaaaaaaaaaa
Login to View More

Abstract

The invention provides a method for forming an alignment mark in a semiconductor process, which comprises the following steps of: etching grooves in a device region and an alignment region at the same time, then forming an epitaxial layer and / or a polycrystalline silicon layer, and using a recess of the epitaxial layer and / or the polycrystalline silicon layer in the alignment region as the alignment mark. Alignment signal attenuation or disappearance caused by the planarization processing process after epitaxy can be avoided, the photoetching step does not need to be additionally added, alignment errors cannot be affected, and the process reliability is improved.

Description

technical field [0001] The present invention relates to a method for forming alignment marks in a semiconductor process. Background technique [0002] In the existing semiconductor process, an alignment mark for photolithography (such as a separate alignment mark, or an alignment mark pattern in the active area mask) is generally formed on the surface of the substrate as a starting step, and then Proceed to other steps. However, for CIS (CMOS Image Sensor) or other processes that require epitaxy before the formation of the active area, after the epitaxy is completed, the shallow alignment marks will be affected by the planarization process, resulting in the attenuation or disappearance of the alignment signal. [0003] In order to solve the alignment problem in the semiconductor process where epitaxy is performed before the active area is formed, a shallow trench can be formed in the alignment area and filled with a dielectric layer as an alignment mark, and then a deep tre...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/68H01L23/544
CPCH01L21/68H01L23/544H01L2223/54426
Inventor 杨瑞坤
Owner GALAXYCORE SHANGHAI