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Novel packaging system chip NPSC architecture based on wireless high-speed bus

A high-speed bus, packaging system technology, applied in the architecture with a single central processing unit, semiconductor/solid-state device components, semiconductor devices, etc., to achieve the effect of high yield, low cost, and wide bandwidth

Pending Publication Date: 2022-08-09
青岛青软晶尊微电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] Aiming at the deficiencies of the prior art, the present invention discloses a new package system chip NPSC architecture based on a wireless high-speed bus, which is used to solve complex system chip CSOC (ComplexSOC) such as VLSI chip pairs connecting subsystems. The contradiction between the data transmission bandwidth requirements of the on-chip high-speed bus and the data transmission bandwidth capability of the actual wired high-speed bus

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  • Novel packaging system chip NPSC architecture based on wireless high-speed bus
  • Novel packaging system chip NPSC architecture based on wireless high-speed bus
  • Novel packaging system chip NPSC architecture based on wireless high-speed bus

Examples

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Embodiment 1

[0049] refer to image 3 As shown, this embodiment provides a novel NPSC architecture of a packaging system chip based on a wireless high-speed bus, which is formed by stacking one or more chiplets on each other or stacking the one or more chiplets and one or more memory dies on each other; Wherein, the one or more chiplets are integrated with a silicon-based optical transceiver IP module, and the silicon-based optical transceiver IP module integrated by the one or more chiplets is connected to the same laser generator.

[0050] One or more chiplets of this embodiment are stacked on top of each other or the one or more chiplets and one or more memory dies are stacked on top of each other or side-by-side on top of an interposer with TSVs.

[0051] In the preferred implementation of this embodiment, an interposer with through-silicon vias is provided on the substrate, and further package bumps are provided on the interposer with through-silicon vias.

[0052] The interposer wit...

Embodiment 2

[0058] On the basis of Embodiment 1, this embodiment uses 2.5D packaging technology to package the new packaging system chip NPSC architecture based on wireless high-speed bus. For details, see Figure 4 , where the stiffener is the stiffener; the Substrate is the substrate; the interposer is the silicon interposer; the bump is the bump; u-bump is the micro-bump.

[0059] In the novel packaged system-on-chip of the present embodiment, chiplets are stacked together or stacked with memory dies, and there is no need to build a complex system-on-chip.

[0060] The 2.5D packaging in this embodiment is an upgrade of the traditional 2DIC packaging technology, which can realize more precise circuit and space utilization.

[0061] In the 2.5D package of this embodiment, the dies are stacked or placed side by side on top of an interposer with through-silicon vias (TSV: ThroughSiliconVia).

[0062] This embodiment has a signal redistribution interconnection layer (RDL) between the dies ...

Embodiment 3

[0065] On the basis of Embodiment 2, this embodiment further uses 3D packaging technology to package the NPSC architecture of the new packaging system chip based on the wireless high-speed bus. For details, see Figure 5 , it can be seen from the cross-sectional view of the 3D package that the vertical interconnection between silicon chips is achieved through metal copper TSVs.

[0066] The 3D package in this embodiment mainly uses metal-metal bonding to realize multi-layer vertical interconnection. The Cu-Sn bonding principle in this embodiment is: after the temperature rises, the metal Sn melts and reacts with Cu to form a metastable metal-to-metal bond. Compound CuSns (melting point 415 ℃), and then Cu, Sns and Cu further react to form the stable intermetallic compound CuzSn251 (melting point 676 ℃).

[0067] In this embodiment, since the melting point of the alloy phase is higher than the Cu-Sn eutectic bonding temperature, when the multilayer chips are stacked, the heatin...

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Abstract

The invention relates to the technical field of integrated circuits, in particular to a novel packaging system chip NPSC architecture based on a wireless high-speed bus, which is formed by mutually stacking one or more small chips or mutually stacking one or more small chips and one or more storage bare chips. Wherein the one or more small chips are integrated with silicon-based optical transceiver IP modules, and the silicon-based optical transceiver IP modules integrated by the one or more small chips are connected with the same laser generator. According to the invention, the small chips are stacked together or the small chips and the storage bare chips are stacked together, a complex system-on-chip does not need to be constructed, a large complex system chip is decomposed into smaller small chips, and compared with a single bare chip, the chip has higher yield and lower cost; the problem of contradiction between the requirement of a super-large-scale integrated circuit chip on the data transmission bandwidth of the on-chip high-speed bus for connecting the subsystems and the data transmission bandwidth capability of an actual wired high-speed bus is solved.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a novel packaged system chip NPSC architecture based on a wireless high-speed bus. Background technique [0002] At the beginning of the 21st century, with the development of integrated circuit manufacturing process technology, integrated circuit design has gradually entered the system-on-a-chip SoC (SystemonaChip). [0003] The system-on-a-chip SoC includes the following characteristics: very large-scale integrated circuits to realize complex system functions; using ultra-deep sub-micron process technology; using one or several embedded CPU cores or digital signal processors (DSP); mainly using third-party IP cores Design. [0004] Among them, the SOC chip architecture based on on-chip high-speed bus is generally such as figure 1 As shown, the current VLSI chips, such as artificial intelligence SOC system chips, generally contain registers in the scale of t...

Claims

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Application Information

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IPC IPC(8): H01L25/18H01L23/48G06F15/78
CPCH01L25/18H01L23/481G06F15/7807H01L2224/48227H01L2224/16225H01L2924/181H01L2224/73204H01L2224/73265H01L2224/32225H01L2924/15311H01L2924/19107H01L2924/00012H01L2924/00
Inventor 陆思安张侠董科
Owner 青岛青软晶尊微电子科技有限公司
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