Field effect transistors with improved implants and method for making such transistors

Abstract

The MOSFET further includes a threshold adjust implant region and / or punch through implant region being aligned with respect to the gate conductor and limited to an area underneath the gate conductor. Such a MOSFET can be made using the following method: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack having the lateral size and shape of a gate hole to be formed; defining the gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; implanting threshold adjust dopants and / or punch through dopants through the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering portions of the semiconductor structure surrounding the gate hole; and removing at least part of the dielectric stack.

Description

technical field [0001] This invention relates generally to metal-oxide-semiconductor field effect transistors (MOSFETs) and, more particularly, to methods of fabricating MOSFETs with improved implants. Background technique [0002] Field effect transistors (FETs) are the basic building blocks of current integrated circuits. Such transistors may be formed in conventional substrates such as silicon substrates or silicon-on-insulator substrates. In both cases, so-called deep implants are introduced into the substrate to improve transistor performance in order to provide heavily doped isolation for complementary metal-oxide (CMOS) integrated circuits, reducing parasitic vertical transistor current gain , and to reduce parasitic latch-up effects, just to mention some of the reasons why deep implants are used. [0003] In CMOS technology, these deep implants are called p-well or n-well deep implants. These p-well or n-well deep implants are required if NMOS transistors (p-well)...

AI Technical Summary

Problems solved by technology

[0008] There is currently no known fabrication scheme for FETs where the threshold-adjust and punch-through implants are well defined and located only below the channel

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