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Low-pass filter and feedback system

A technology of low-pass filter circuit and filter circuit, which is applied in the direction of electrical components, impedance converters, automatic power control, etc., can solve the problems of increasing circuit area and difficulty in using MOS capacitors, achieve miniaturization of manufacturing costs, and reduce manufacturing costs. cost effect

Inactive Publication Date: 2005-02-09
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as described above, in the loop filter specified in the previous application, it is difficult to form the capacitive element 33 using a MOS capacitor.
Therefore, the capacitive element 33 is configured using, for example, inter-wiring capacitance, which becomes a factor for increasing the circuit area.

Method used

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  • Low-pass filter and feedback system
  • Low-pass filter and feedback system
  • Low-pass filter and feedback system

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment

[0052] figure 1 The configuration of the feedback system according to the first embodiment of the present invention is shown. The feedback system involved in this embodiment is a PLL, including: a phase comparator 10 , a charge pump circuit 20A, a loop filter 30A, a voltage controlled oscillator 40 as an output clock generator, and a frequency divider 50 . Wherein, the phase comparator 10, the voltage controlled oscillator 40 and the frequency divider 50 are as described above. Hereinafter, the charge pump circuit 20A and the loop filter 30A will be described in detail.

[0053] The charge pump circuit 20A includes charging current sources 21 and 23 that supply currents αIp and (1−α)Ip, and discharging current sources 22 and 24 . Then, when the signal UP is supplied, the control switches SW1 and SW3 are turned on, and the currents αIp and (1-α)Ip are discharged. And if the signal DN is provided, the control switches SW2 and SW4 are turned on, and the currents αIp and (1−α)...

no. 2 Embodiment

[0067]In the loop filter 30A according to the first embodiment, since the capacitive element 31 and the capacitive element 33 are connected in series, the voltage of the input terminal IN1 is divided and applied to the capacitive elements 31 and 33 respectively. Therefore, if the voltage Vth of the power supply 34 is raised too high, the voltage applied to both ends of the capacitive element 31 will be relatively low on the contrary. Furthermore, if this voltage falls below the threshold voltage of the MOS transistor, it becomes difficult to configure the capacitive element 31 using a MOS capacitor. Therefore, it is considered that a loop filter having the same filter characteristics as conventional ones is realized by connecting the capacitive element 31 and the capacitive element 33 in parallel.

[0068] Figure 5 The configuration of the loop filter according to the second embodiment of the present invention is shown. The loop filter 30B according to this embodiment inclu...

no. 3 Embodiment

[0091] In the second embodiment, when there is a clear linearity between the output voltage Vout of the loop filter 30B and the oscillation frequency of the voltage controlled oscillator 40, and it is not necessary to increase the oscillation frequency of the voltage controlled oscillator 40 In the case of a change, a power supply outputting a constant voltage may be used instead of the voltage buffer circuit 35 and connected to the resistance element 32. Hereinafter, a loop filter configured by using a power supply in the loop filter 30B instead of the voltage buffer circuit 35 will be described.

[0092] Figure 9 The structure of the loop filter according to the third embodiment of the present invention is shown. The loop filter 30C according to this embodiment includes: a capacitor element 31 as a first element block, a resistor element 32 and a power supply 34 connected in series as a second element block, a capacitor element 33 as a third element block, and a capacitor ...

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Abstract

Low-pass filter and feedback system. To decrease the size of a capacitive element while maintaining, in a low-pass, the filter characteristics equivalent to those of a conventional low-pass filter, to stably operate the low-pass filter and further, to use a MOS capacitor as a capacitive element. In the low-pass filter including a first capacitive element (31), and a resistive element (32) and a second capacitive element (33) which are connected in series to the first capacitive element, a first electric current (Ip / 10) is supplied to a first input terminal (IN1) connected to one end of the first capacitive element (31), and a second electric current (9Ip / 10) is supplied to a second input terminal (IN2) connected to the other end. Herein, the capacitance value of the first capacitive element (31) is set according to the magnitude of the first electric current. Further, the resistive element (32) is provided with a power supply (34) that is connected in series to the resistive element, and a voltage equal to or higher than the threshold voltage of a MOS transistor is always applied between the second input terminal (IN2) and the ground.

Description

technical field [0001] The invention relates to a low-pass filter circuit, in particular to the technology of a low-pass filter circuit which is more suitable for a loop filter in feedback systems such as a phase synchronous circuit and a delay-locked loop circuit. Background technique [0002] Feedback systems, especially phase synchronization circuits (hereinafter referred to as PLLs), are now becoming indispensable components of semiconductor integrated circuit systems, and almost all LSIs are equipped with phase synchronization circuits. Moreover, its application range spans various fields such as communication equipment, microprocessors, and IC cards. [0003] Figure 14 Shows the structure of a general charge pump type PLL. Referring to this figure, the outline of the PLL will be described. The phase comparator 10 compares the phase difference between the input clock CKin supplied to the PLL and the feedback clock CKdiv, and outputs a signal UP and a signal DN corres...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H11/04H03H7/06H03H11/12H03H11/40H03L7/089H03L7/093
CPCH03H7/06H03H11/1213H03H11/126H03H11/405H03L7/0893H03L7/093H03H11/04
Inventor 道正志郎森江隆史曾川和昭
Owner PANASONIC CORP