Solid-state imaging device and camera
A technology of solid-state imaging device and imaging area, which is applied to electric solid-state devices, semiconductor devices, electrical components, etc., can solve problems such as leakage current leakage and large noise, and achieve the effect of reducing noise and high practical value.
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no. 1 approach
[0037] Figure 4 It is a cross-sectional view showing an example of the structure of an n-channel MOS transistor and a trench element isolation portion constituting the imaging region of the MOS solid-state imaging device 110 according to the first embodiment of the present invention. The MOS transistor is separated from the adjacent MOS transistor by the element isolation part 2 , and the photodiode 3 forms an n-type diffusion region in the silicon wafer (or P-type well) 1 . The photodiode 3 also serves as the source of the MOS transistor in the imaging region, and an element isolation portion 2 is formed in a region adjacent to the photodiode 3 like other MOS transistors.
[0038] Furthermore, it is desirable to form a p-type diffusion region as the dark current suppressing layer 6 in the vicinity of the surface of the n-type diffusion region which is the photodiode 3 . In this case, the dark current suppression layer 6 such as Figure 4 As shown, it extends to the periphe...
no. 2 approach
[0056] In the MOS solid-state imaging device according to this embodiment, the imaging region and peripheral circuits are constituted by a plurality of MOS transistors electrically isolated by an element isolation section. Figure 10 It shows the structure of the element isolation part between the MOS transistors in the imaging area or in the peripheral circuit, and is a cross-sectional view showing that the transistor 40 and the transistor 41 are electrically isolated by the element isolation part 42 . The element isolation portion 42 erodes the silicon wafer 1 to a depth of not less than 1 nm and not more than 200 nm, which can generate leakage current between the active region 43 of the transistor 40 and the active region 44 of the transistor 41 . Such as Figure 10 As shown, the impurity diffusion layer 45 for suppressing leakage is provided directly under the element isolation portion 42, thereby improving the breakdown voltage related to the leakage current between the t...
no. 3 approach
[0058] Figure 11 An example of the structure of an element isolation portion between MOS transistors constituting the imaging area or in the peripheral circuit in the MOS solid-state imaging device according to the third embodiment is shown, and it shows that the transistor 46 and the transistor 47 are electrically connected through the element isolation portion 48. Cutaway view of what it looks like in isolation. As described above, the crystal structure of the interface between the element isolation portion 48 and the silicon wafer 1 is in a disordered state, and leakage current occurs. Therefore, on the silicon wafer 1 side of the interface between the element isolation portion 48 and the silicon wafer 1 formed, the impurity diffusion layer 51 is formed along the interface between the element isolation portion sidewall and the silicon wafer 1, thereby suppressing the formation of the element isolation portion 48. The interface level leakage with silicon chip 1.
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