Manufacturing method of gate pole structure with metal layer lateral surface part removed

Abstract

A method for making gate structure contains providing a silicon substrate, forming conductive layer on silicon substrate, forming metal layer on conductive layer, forming the per-patterned first protective layer on metal layer wherein every gate pattern has exposed top and side surface, removing part of side surface to form first gate assembly, transferring the pattern of first gate assembly to metal layer to form the second gate assembly, on the substrate, the exposed of first and second gate assembly forming the second protective layer, transferring the first gate assembly and pattern of second gate assembly to conductive layer to form third gate assembly. Said invention ca avoid the improper short circuit between bit line metal layer and gate metal layer without generating cavity in insulation layer between gates.

Description

【Technical field】 [0001] The present invention relates to a method for manufacturing a semiconductor memory, and more specifically, relates to a method for manufacturing a gate structure of a semiconductor memory. 【Background technique】 [0002] In the traditional semiconductor memory manufacturing process, the contact structure is often formed through the contact window, so that the relevant components can achieve the necessary electrical connection. Such as figure 1 As shown, the bit line contact structure formed by, for example, the DRAM semiconductor memory manufacturing process mainly includes: a substrate 11 usually made of silicon, a conductive layer 12 usually made of polysilicon (Poly-Si), and usually made of tungsten silicide (WSi). A metal layer 13, a protective layer 14 usually made of silicon nitride (SiN), an insulating layer 15 usually called a spacer usually made of silicon nitride, a barrier layer 16 usually made of silicon nitride, Insulating layer 17, us...

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Problems solved by technology

[0004] Although this method can improve the short circuit problem, because the parts on both sides of the gate metal layer 13 are removed, the insulating layer 15 and the barrier layer 16 will form an arc-shaped part concave to the side of the metal layer 13, thereby making the insulation between the gate electrodes When layer 17 is formed it will produce figure 1 The holes 171 shown degrade the insulation and adversely affect the electrical properties of the overall structure

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