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Semiconductor device

A semiconductor and conductivity technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., and can solve problems such as insufficient variation

Inactive Publication Date: 2005-05-25
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is, even if a strong substrate bias is applied during standby of the MIS transistor, the change amount ΔVth of the threshold voltage Vth during standby is not sufficiently large during operation.

Method used

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Examples

Experimental program
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Effect test

no. 1 approach

[0049] figure 1 (a) and (b) are cross-sectional and plan views of a heterojunction p-channel VTMIS transistor (hereinafter referred to as pHVTMISFET) using the SiGe layer of the first embodiment of the present invention as a channel.

[0050] Such as figure 1 (a) and (b) show that the pHVTMISFET of this embodiment includes a p-type Si substrate 10, a Si buffer layer 13 with a thickness of about 10 nm epitaxially grown on the Si substrate 10 by UHV-CVD, and a Si buffer layer 13 on the Si buffer layer 13. A SiGe film 14 with a thickness of about 15 nm (30% Ge occupancy) epitaxially grown by UHV-CVD and a Si gap layer 15 with a thickness of about 5 nm epitaxially grown on the SiGe film 14 by UHV-CVD.

[0051] Further, the pHVTMISFET includes a gate insulating film 16 formed of a silicon oxide film with a thickness of about 6 nm provided on the Si gap layer 15 and a gate electrode 17 provided on the gate insulating film 16 . The gate electrode 17 is made of polycrystalline silic...

no. 2 approach

[0099] In this embodiment mode, an example in which the present invention is applied to a complementary HVTMIS device (cHVTMIS device) having a SiGe channel will be described.

[0100] Figure 13 (a), (b), and (c) are diagrams showing the configuration of the cHVTMIS device of the present embodiment, Figure 13 (a) is a cross-sectional view showing the structure of the cHVTMIS device of this embodiment, Figure 13 (b) is an energy band diagram showing the band state of pHVTMISFET when a gate bias voltage is applied (during operation), Figure 13 (c) is an energy band diagram showing the band state of the nHVTMISFET when a gate bias is applied (during operation).

[0101] Such as Figure 13 As shown in (a), the cHVTMIS device of this embodiment has a p-type Si substrate 10, an embedded oxide film 11 formed by implanting oxygen ions into the Si substrate, etc., and a p-channel type oxide film 11 formed on the embedded oxide film 11. The semiconductor layer 30 for the HVTMISF...

no. 3 approach

[0110] In the above-mentioned first and second embodiments, although the channel region is made of SiGe, the channel region may be made of SiGeC having a C (carbon) occupancy of 0.01% to 2% (for example, about 1%). If a small amount of C is added to the SiGe channel region, the effect is further enhanced. Although SiGe crystals tend to have a strong tendency to cause undesired changes in the crystal structure due to ion implantation, by constituting the channel region with SiGeC, undesired changes in the crystal structure due to ion implantation can be suppressed.

[0111] Figure 14 (a), (b), and (c) are diagrams showing the configuration of the cHVTMIS device of the present embodiment, Figure 14 (a) is a cross-sectional view showing the structure of the cHVTMIS device of this embodiment, Figure 14 (b) is an energy band diagram showing the band state of the pHVTMISFET when a gate bias is applied (during operation), Figure 14 (c) is an energy band diagram showing the ban...

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Abstract

The semiconductor device of the present invention includes a semiconductor layer (10-15), a gate insulating film (16) provided on the semiconductor layer, a gate electrode (17) provided on the gate insulating film, and in the semiconductor layer A source region (20a) and a drain region (20b) of the first conductivity type provided on both sides of the gate electrode are viewed from a plan view, and between the source region and the drain region in the semiconductor layer, The gap layer (25), the channel region (24) and the region below the channel (23, 22) of the second conductivity type arranged in sequence downward from the interface with the above-mentioned gate insulating film, and the application to the above-mentioned channel below the region A bias electrode part (Vbs) for voltage, wherein the channel region is composed of a first semiconductor, and the gap layer and the region below the channel are respectively composed of a second semiconductor and a third semiconductor having a band gap larger than that of the first semiconductor, The above-mentioned bias electrode member is provided independently of the above-mentioned gate electrode and capable of applying a voltage.

Description

technical field [0001] The present invention relates to a semiconductor device including a heterojunction type MIS transistor, and more particularly to a semiconductor device in which the operation speed is maintained and the voltage is lowered. Background technique [0002] In recent years, portable information terminal devices driven by batteries have been widely used. In such devices, in order to prolong the battery life, it is strongly desired to maintain high-speed operation and reduce the power supply voltage. [0003] Here, power consumption (P load) of a circuit composed of complementary MIS devices (cMIS devices) is mainly generated by charge and discharge of a load, and is represented by the following equation (1). [0004] P load=f·C load·VDD 2 (1) [0005] Here, f is the driving frequency of the load, C load is the load capacitance, and VDD is the power supply voltage. From the above equation (1), it can be seen that lowering the power supply voltage VD...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L21/84H01L27/12H01L29/778H01L29/80
CPCH01L21/823807H01L21/84H01L27/1203H01L29/7782H01L29/802H01L29/1029
Inventor 高木刚
Owner PANASONIC CORP
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