High-speed low clock signal oscillation amplitude driving conditional precharging CMOS trigger

Abstract

A high and low clock signal amplitude pre-fill CMOS trigger characterizes in connecting substrates of all PMOS tubes in the first stage latch of SAFF-CD conditional pre-fill structure driven by the low voltage amplitude clock signals to the power supply directly, the same time when omitting the only grating connected with NMOS tubes of the same supply end, two coupled NMOS tubes at the drain are removed, so that the drain of NMOS tubes with the substrate and the source all connected with the earth is connected with the drain of two remained NMOS tubes, finally, two compensated output ends of the first state latch are connected with two mutual independent single clock phase latches with the same circuit parameters.

Description

technical field [0001] The technical field of direct application of the "high-speed low clock signal swing condition precharge CMOS flip-flop" is the low power consumption flip-flop circuit design driven by low clock signal swing. The proposed circuit is a kind of low-power CMOS flip-flop circuit unit suitable for low-swing clock signal network technology. Background technique [0002] With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of the entire circuit; among them, in the working state of the circuit, the energy consumed in the clock interconnec...

AI Technical Summary

Problems solved by technology

However, the problem with the SAFF_CP circuit is that since the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and falling edge of the output of the flip-flop circuit will be extremely different. Symmetry, which poses potential problems for the use of circuit cells

It can be seen that for the SAFF_CP circuit that uses a cross-coupled NAND2 latch circuit as the output terminal, the output terminal signal will always have a delay of one gate more than the rising edge inversion when the falling edge of the output signal occurs, thus causing the rising edge delay of the circuit and The problem of asymmetrical falling edge delay

At the same time, since the SAFF_CP circuit adopts the conditional precharge structure, the NMOS transistors MN2, MN3 and MN4 in the circuit become redundant transistors, which not only increases the power consumption of the circuit, but also increases the internal node capacitance of the circuit, which limits the working speed of the circuit

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