Method of increasing packing density of phase change storage and its implementing circuit

Abstract

This invention relates to a method and a circuit for increasing the storage density of the phase-transition storage, in which, multiple storage units share one gate device (a diode, a triode and a field-effect transistor) to reduce the areas occupied by the storage units. A hierarchical bit line design is applied to the circuit system and the bit line is connected with the read out amplifier and a write drive circuit by a multi-stage multiple selector to increase the reliability of read and write operation.

Description

technical field [0001] The invention belongs to the technical field of large-scale digital integrated circuits, and specifically relates to a method for increasing the storage density of a resistive memory by multiplexing gate tubes and a realization circuit thereof. Background technique [0002] Memory occupies an important position in the semiconductor market. Only DRAM (Dynamic Random Access Memory) and FLASH occupy 15% of the entire market. With the continuous popularization of portable electronic devices, the non-volatile memory market is also growing. Flash memory technology (FLASH) is currently the mainstream product in the non-volatile memory market, but the floating gate used to store charges in FLASH cannot be reduced indefinitely with the development of technology generations, so there must be a new generation of non-volatile memory as the foundation of flash memory technology. replacement. As an emerging non-volatile storage technology, phase change memory has s...

AI Technical Summary

Problems solved by technology

To increase the integration density, it is necessary to reduce the width-to-length ratio of the gate transistor. However, the reduction of the width-to-length ratio means that more voltage is dropped on the gate transistor, so that the write voltage provided by the write driver is required to be large enough, which requires Some voltage boosting modules (such as charge pumps), which will increase the complexity of the circuit design

like Figure 5 It is a cross-sectional view of the structure of a 1T1R memory cell. The memory cell is above the MOS gate, so the area occupied by a single memory cell is determined by the area of ​​the active device. From the previous analysis, it can be known that the area of ​​the active device is affected by the operation Current constraints cannot be minimized, so the integration density cannot be further improved under a certain operating current node

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