Multi-scanning chain LSI circuit test data compressing method

Abstract

The present invention relates to a large scale integrated circuit test data compression method of multiple scanning chains. It is characterized by that it utilizes restricted input compaction to make width compression, and utilizes LFSR and folding counter codification to make two-dimensional compression.

Description

Technical field: [0001] The invention relates to an integrated circuit test technology, in particular to a test data compression method in a built-in self-test (Built-In Self-Test) method for a VLSI with multiple scan chains. technical background: [0002] The development of integrated circuit technology makes it possible to integrate hundreds of millions of devices in a chip, and can integrate pre-designed and verified IP cores, such as memory cores, microprocessor cores, DSP cores, etc. This diversified integrated chip has become an integrated system capable of processing various information, and is called a system on chip or system chip SOC. SOC greatly reduces the system cost, shortens the design cycle, and speeds up the time to market. However, the testing of SOC products faces more and more challenges, such as: [0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested ...

AI Technical Summary

Problems solved by technology

[0003] 1. There are few test points on the chip, and the test points that can be directly controlled or observed are limited. Usually, it can only be tested through the limited input/output pins of the chip, and it is difficult to directly control or observe the internal nodes of the chip through macro mechanical devices.

[0004] 2. The automatic test equipment ATE is expensive, and the development speed of chip design and manufacturing technology i

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