Method for controlling roughness of silicon crystal substrate material surface

A technology of surface roughness and substrate material, which is applied in the control field of surface roughness of silicon single crystal substrate material, can solve the problem of high surface roughness of substrate sheet, and achieves improvement of uniformity and exchange rate, improvement of flatness and stability. good effect
CN1864926AInactive Publication Date: 2006-11-22HEBEI UNIV OF TECH

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
HEBEI UNIV OF TECH
Publication Date
2006-11-22
Estimated Expiration
Not applicable · inactive patent
Patent Text Reader

Abstract

The invention relates to a method for controlling the surface roughness of silicon single-crystal liner material. According to the chemical property of silicon single-crystal liner material, the invention selects alkali medium; uses SiO2 hydrosol as abrasive; uses pH adjuster to adjust the pH value of solution 9-13.5; adds surface activator as FA / O to prepare the polish liquid. The invention uses two polishing steps as roughly polishing and finely polishing at different polishing conditions; roughly polishes for 10-20mins while the flux is 100-200ml / min, the temperature is 30-40Deg. C, the rotation speed is 40-120rpm and the pressure is 0.10-0.20MPa; finely polishing for 4-7mins while the flux is 800-1000ml / min, the temperature is 20-30Deg. C, the rotation speed is 30-60rpm, and the pressure is 0.05-0.10MPa. The invention can realize low roughness of single-crystal liner material.
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Description

technical field

[0001] The invention relates to a chemical mechanical polishing method, in particular to a method for controlling the surface roughness of a silicon single crystal substrate material. Background technique

[0002] At present, silicon single crystal is the main substrate material of IC. As the integration level of IC continues to increase, the feature size continues to decrease, and the requirement for the perfection of the silicon wafer surface is getting higher and higher. Because the particles and metal impurities on the surface of the polished sheet will seriously affect the breakdown characteristics, interface state and minority carrier life, especially for the surface effect type MOS large-scale integrated circuits, so the smoothness of the surface of the polished sheet, Defects, roughness, metal contamination and particles have extremely stringent requirements and controls. For example, in the production of DRAM devices with a line width of 64M and 0.3...

Claims

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