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A method for depositing a metal layer on a semiconductor interconnect structure

A technology for depositing metal layers and interconnection structures, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., and can solve problems such as poor adhesion of metal materials and loss of revenue

Inactive Publication Date: 2007-04-11
上海佑磁信息科技有限公司
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Problems solved by technology

In fact, sellers of deposition tools expressly discourage the use of argon sputtering on metal layers, both because of concerns about short-circuiting of the protective layer, and because the metal material covering the dome of the sputtering chamber does not adhere well and eventually flakes off to subsequent on wafers, resulting in lost revenue due to excess foreign material

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  • A method for depositing a metal layer on a semiconductor interconnect structure
  • A method for depositing a metal layer on a semiconductor interconnect structure
  • A method for depositing a metal layer on a semiconductor interconnect structure

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Embodiment Construction

[0026] Referring in more detail to the drawings, and in particular to FIGS. 1A to 1D , a first embodiment of the process according to the invention is illustrated. Referring first to FIG. 1A , two layers of a semiconductor wafer 10 are shown. The first layer includes an interlayer dielectric (ILD) layer 12 . For clarity, the underlying silicon is not shown. In the next layer, ILD 18 is deposited on top of ILD 12 using conventional techniques.

[0027] Any dielectric material can be used to make ILD 12 and ILD 18 . However, today's submicron high-density integrated circuit requirements require that IDLs 12 and 18 preferably constitute organic dielectric layers, and more preferably low-k organic dielectric layers, i.e., have a low Permittivity of organic dielectric materials. A preferred example of such a low-k organic dielectric material is SiLK (poly(arylene ether) from Dow Chemical Company). The composition of ILDs 12 and 18 is not limited to organic low-k dielectrics. ...

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Abstract

Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a dielectric layer. The dielectric layer is patterned so as to expose the metal conductor. A liner layer is then deposited into the pattern. The liner layer is then argon sputter etched to remove the liner layer and expose the metal conductor. In the process of argon sputter etching, the liner layer is redeposited onto the sidewall of the pattern. Lastly, an additional layer is deposited into the pattern and covers the redeposited liner layer.

Description

[0001] Cross References to Related Applications [0002] This application is related to US Patent Application Serial No. 10 / 318,606, entitled "Method of Depositing a Metal Layer on a Semiconductor Interconnect Structure Having a Capping Layer," filed on the same date as this application. technical field [0003] The present invention relates to semiconductor processing, and more particularly to semiconductor wafer processing including advanced interconnect structures using non-ferrous metallurgy. Background technique [0004] Advanced interconnect structures using non-ferrous metallurgy present several technical challenges with regard to functional properties. Among the most important are obtaining stable low contact resistance under thermal cycling, and good reliability under electromigration and stress migration. [0005] Electromigration is the movement of ions within a conductor such as copper in response to an electric current passing therethrough, and can eventually l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01LH01L21/28H01L21/4763
CPCH01L21/76865H01L21/76805H01L21/76844H01L21/28
Inventor 桑德拉·马霍特拉安德鲁·西蒙
Owner 上海佑磁信息科技有限公司
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