Storage cell, pixel structure and manufacturing method of storage cell
A storage unit and pixel structure technology, applied in optics, instruments, transistors, etc., can solve problems such as inability to apply transmissive liquid crystal display panels, influence of aperture ratio, crowded circuit layout, etc.
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no. 1 example
[0085] 3A and 3B are schematic diagrams of the storage unit in the first embodiment of the present invention. Referring to FIG. 3A , the memory unit 300 of this embodiment is suitable to be disposed on a substrate A, and the substrate A is, for example, a glass substrate or other transparent substrates. The memory unit 300 of this embodiment includes an island polysilicon layer 310 , a first dielectric layer 320 , a floating layer 330 , a second dielectric layer 340 and a control gate 350 . Wherein, the island-shaped polysilicon layer 310 is disposed on the substrate A, and the island-shaped polysilicon layer 310 includes a source doped region 312, a drain doped region 314, and a doped source region 312 and a drain doped region 314. The channel area 316, and the surface of the channel area 316 has a plurality of regularly arranged tips 316a. The first dielectric layer 320 is disposed on the island polysilicon layer 310, the floating layer 330 is disposed on the first dielectr...
no. 2 example
[0101] 5A and 5B are schematic diagrams of a storage unit in a second embodiment of the present invention. Please refer to FIG. 5A and FIG. 5B at the same time. The memory cell 300' of this embodiment is similar to the first embodiment, but the main difference between the two is that the control gate 350' of this embodiment is located in the source doped region 312. A part of the region, a part of the region of the doped drain region 314 and above the channel region 316 . In other words, the width W2 of the control gate 350' in this embodiment is greater than the length L of the channel region 316.
[0102] In the memory cell 300' of this embodiment, since the control gate 350' partially overlaps the source doped region 312 and the drain doped region 314, and the source doped region 312 and the drain doped region 314 The dopant concentration of the channel region 316 is higher than that of the channel region 316, so compared with the first embodiment, the memory cell 300' of ...
no. 3 example
[0105] 7A, 7B and 7C are schematic diagrams of the storage unit in the third embodiment of the present invention. Please refer to FIG. 7A, FIG. 7B and FIG. 7C at the same time. The memory cell 300" of this embodiment is similar to that of the first embodiment, but the main difference between the two is that: the island-shaped polysilicon layer 310 of this embodiment also includes The charge-induced doped region 318 between the drain doped region 314 and the charge-induced doped region 318 is located under the control gate 350 ′.
[0106] It can be seen from FIG. 7B and FIG. 7C that the width W3 of the charge-induced doped region 318 is smaller than the width W4 of the channel region 316 (shown in FIG. 7B ), or equal to the width W4 of the channel region 316 (shown in FIG. 7C ). , and the charge-inducing doped region 318 is, for example, a P-type doped region. It should be noted that since the charge-induced doped region 318 is a P-type doped region and the drain doped region ...
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Abstract
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