Assembly platform

Abstract

An assembly platform for arrangement as an interposer device between an integrated circuit and a substrate to interconnect the integrated circuit and the substrate through the assembly platform, the assembly platform comprising: an assembly substrate; a plurality of conducting vias extending through the assembly substrate; at least one nanostructure connection bump on a first side of the assembly substrate, the nanostructure connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate, wherein each of the nanostructure connection bumps comprises: a plurality of elongated conductive nanostructures vertically grown on the first side of the assembly substrate, wherein the plurality of elongated nanostructures are embedded in a metal for the connection with at least one of the integrated circuit and the substrate, at least one connection bump on a second side of the assembly substrate, the second side being opposite to the first side, the connection bump being conductively connected to the vias and defining connection locations for connection with at least one of the integrated circuit and the substrate.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This Application is a Section 371 National Stage Application of International Application No. PCT / SE2017 / 050430, filed May 3, 2017 and published as WO 2017 / 192096 on Nov. 9, 2017, in English, which claims the benefit of priority of Swedish Application No. 1630103-8, filed on May 6, 2016, the entire contents of which are hereby incorporated by reference in their entirety.FIELD OF THE INVENTION[0002]The present invention relates to an assembly platform for arrangement between an electronic device and a substrate to interconnect the first electronic device and the substrate through the assembly platform. The present invention also relates to a method of manufacturing such an assembly platform.BACKGROUND OF THE INVENTION[0003]In today's electronics, size and form factors are of significant consideration in any physical arrangement of chips. Due to the rapid progress in portable electronic devices the demand for more compact physical arrangemen...

AI Technical Summary

Benefits of technology

The use of nanostructure connection bumps increases I / O density, reduces signal propagation delays, and enhances mechanical and electrical reliability, allowing for more compact and high-performance electronic assemblies with improved thermal dissipation and mechanical support.

Problems solved by technology

However, the potential of the today's conventional interposers faces the limitations on the number of devices that can be connected.

For example, the interposer may limit the form factor and / or the performance of a final electronic device since the number of components that can be interconnected is primarily limited by the interposer solder balls and its limitations in terms of size, pitch (a typical conventional pitch may be about 50 μm) and height.

The conventional interposers are relatively ‘unsmart’ which do not allow anything more than the interconnects and routing paths.

The I / O points or pillars made by the conventional technology also possess challenges to further miniaturize the I / O dimensions and increases the poor reliability issues and fatigue failures.

Accordingly, todays conventional interposers pose a limitation on the number devices that can be connected due to the arrangement of the solder balls or the metallic materials that creates the connection.

This may lead to that the interposer may limit the performance of a final electronic device since the number of components that can be interconnected is set by the interposer solder ball and its limitations.

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