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Substrate processing method and substrate processing apparatus

a substrate processing and substrate technology, applied in the direction of photosensitive material processing, transportation and packaging, coatings, etc., can solve the problem that the air down flow described above is not able to remove the impurities of molecule level, and achieve the effect of improving the uniformity of line width

Inactive Publication Date: 2005-06-16
TOKYO ELECTRON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a substrate processing method and apparatus that improves the uniformity of line width even in the presence of impurities of molecule level. The method involves coating a resist on the substrate and placing it in an atmosphere including a vapor. By deliberately placing the substrate in the vapor and controlling the pressure, the amount of moisture adhered to the substrate can be controlled, resulting in improved exposure and increased uniformity of line width. The substrate processing method and apparatus of the present invention can provide a more uniform and consistent substrate for exposure and improve the overall performance of the substrate processing process.

Problems solved by technology

The down flow of the air described above is not able to remove the impurities of molecule level.

Method used

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  • Substrate processing method and substrate processing apparatus
  • Substrate processing method and substrate processing apparatus
  • Substrate processing method and substrate processing apparatus

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Experimental program
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Effect test

first embodiment

[0039]FIG. 4 is a sectional view of the vapor processing unit 30 relating to the above-mentioned In this vapor processing unit 30, for example, on an upper portion of cylindrically shaped holding table 34, provided for holding the wafer W, for example, a cylindrically shaped lid 32 is disposed. A lifting mechanism 26 configured of an air cylinder enables the lid 32 to be lifted and lowered. An O-ring for seal is attached to the lower end of the lid 32. When the lid 32 is lowered by the lifting mechanism 26, a processing chamber R is formed as the lower end portion thereof touches the holding table 34.

[0040] A plurality of holes 34a, for example three, pierces through the holding table 34. Three Support pins 29 supporting the wafer W from the back side are provided and a lifting cylinder 36 enables the support pins 29 to protrude and sink to the surface of the holding table 34 through the holes 34a. Thereby, the wafer W can be delivered to and received from the wafer transfer mechan...

second embodiment

[0048]FIG. 6 is a sectional view showing a vapor processing unit according to the present invention. Incidentally in FIG. 6, the same numerals and symbols will be used to designate the same components as those in FIG. 4, and the explanation thereof will be omitted. A heating plate 43 heating the wafer W by placing the wafer W thereon is disposed on the holding table 41 in the vapor processing unit 40. The heating plate 43 has, for example, a heater 45 and the wafer W is heated thereby. On the heating plate 43, three holes 43a are formed and the supporting pins 29 protrude and sink therethrough. With such configuration, the wafer W can be delivered and received from the outside. Meanwhile, a supply port 41a for supplying the vapor from the vapor generator 35 into the processing chamber R is formed on the holding table 41.

[0049] With regard to the processing steps of the vapor processing unit 40, first of all, the wafer W is placed on the heating plate 43 and the lid 32 is lowered to ...

fourth embodiment

[0054]FIG. 9 is a sectional view showing a vapor processing unit according to the present invention. Incidentally, in FIG. 9, the same numerals and symbols will be used to designate the same components as those in FIG. 4, and the explanation thereof will be omitted. In the central portion of the lid 32 in the vapor processing unit 60, an air supply port 32b is formed for supplying air into the processing chamber R from the air supply source 54 through a supply pipe 57. The air from the air supply source 54 is supplied heated, for example, with a heater 55 to a predetermined temperature, for example, 50° C. to 100° C. On the inside ceiling of the lid 32, a defusing member 56 is attached for defusing the air supplied as above uniformly inside the processing chamber R. A plurality of small holes 56a are formed on the defusing member 56. In such manner, the air spreads out as far as the edge of the wafer W.

[0055] Furthermore, although not illustrated, similar to each of the aforesaid em...

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Abstract

The wafer coated with the resist is deliberately placed in the vapor before being transferred to an aligner that exposes the resist on the wafer, the vapor, for example, the moisture, uniformly adheres onto the resist on the wafer. As a result, the substrate can uniformly be exposed in the following exposing process, and the uniformity of the line width and the like can be improved.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a substrate processing apparatus for coating a semiconductor wafer with a resist and developing thereof in a fabrication of semiconductor device. In detail, the invention relates to a substrate processing apparatus that controls the atmosphere of the processing environment of the substrate. [0003] 2. Description of the Related Art [0004] In a process of photolithography in the semiconductor device fabrication, the surface of a semiconductor wafer (hereinafter referred to as “a wafer”) is coated with a photo-resist, exposing a mask pattern on the resist, then developing thereof, forming a resist pattern on the wafer surface. The resist coating and development are performed in an integrated coating and developing processing apparatus including a thermal processing apparatus such as a heating processing apparatus or a cooling processing apparatus. The coating and developing apparatus is...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/00H01L21/027H01L21/677G03F7/38
CPCH01L21/67178H01L21/67751H01L21/67748
Inventor MATSUI, HIDEFUMIKITANO, JUNICHI
Owner TOKYO ELECTRON LTD
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