Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate; forming a to-be-doped material layer and a top hard mask layer located on the to-be-doped material layer on the substrate; performing one or more patterning processing on the top hard mask layer, the patterning processing comprising: forming a pattern structure layer on the top hard mask layer; etching the top hard mask layer by taking the graphic structure layer as a mask to form a mask opening; and removing the pattern structure layer; and after the last time of patterning processing is completed, doping ions into the to-be-doped material layer exposed out of the mask opening, and taking the to-be-doped material layer doped with ions as a target pattern layer. The etching resistance of the top hard mask layer is high, so that in the process of forming the mask opening, the influence of transverse etching on the side wall of the mask opening is small, the perpendicularity and flatness of the side wall of the mask opening are improved, the line width uniformity of the target pattern layer is correspondingly improved, and the pattern transmission precision is further improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (integrated circuit, IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and development in the direction of higher complexity. [0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit fabrication. [0004] At present, how to improve the matching degree b...

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Problems solved by technology

[0003] During the development of integrated circuits, usually while the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) gradually decreases, which increases accordingly. Difficulty and complexity of integrated circuit manufacturing

[0004] At present, in the case of shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge

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