SRAM device

Abstract

In a CMOS type SRAM device having a 6-transistor configuration, only a drive transistor and an access transistor of one unit circuit are designed with a larger size, with the other four transistors having a smaller size.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to an SRAM (static random access memory) device in which memory cells can be arranged with a high density. [0002] A CMOS type SRAM device having a 6-transistor configuration is known in the art. Such an SRAM device includes two unit circuits, each including a PMOS load transistor, an NMOS drive transistor and an NMOS access transistor. The PMOS load transistor and the NMOS drive transistor together form an inverter, and the NMOS access transistor connects the output of the inverter to a bit line. The two unit circuits are coupled together by connecting the input and the output of one inverter with those of the other inverter in a cross-coupled manner. [0003] An SRAM device described in U.S. Pat. No. 5,744,844 (first conventional example) employs a lateral-type cell structure in which the PMOS load transistor of each unit is provided in an N-well region that is located in a central area of a memory cell region, the NMOS...

AI Technical Summary

Benefits of technology

This configuration achieves a significant increase in cell current, reduces bit line amplification delay, and minimizes cell area while maintaining data integrity, with a cell current more than three times that of prior art and leak currents reduced to half.

Problems solved by technology

A smaller cell current means a greater bit line amplification delay.

However, in the first conventional example, the two unit circuits are symmetric in terms of the size of the constituent transistors, whereby in order to increase the cell current to reduce the bit line amplification delay so as to realize a faster operation, it is necessary to increase the size of all of the six transistors, which leads to a substantial increase in the cell area.

In the second conventional technique, the NMOS access transistors of the two units have the same gate width, whereby the current driving power of the NMOS drive transistor having a large gate width cannot be fully made use of.

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