Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Description

CROSS REFERENCES TO RELATED APPLICATION [0001] The present invention contains subject matter related to Japanese Patent Application JP 2004-067489 filed in the Japanese Patent Office on Mar. 10, 2004, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor integrated circuit, more particularly relates to a semiconductor integrated circuit achieving a reduction of power consumption by using a transistor having a high threshold voltage to cut the supply of power to an unused circuit. [0004] 2. Backgound Art [0005] The power supply voltage of semiconductor integrated circuits have fallen year by year along with the reduction of the power consumption and the miniaturization of processing dimensions. When a signal amplitude becomes small due to the reduction of the power supply voltage, the threshold voltage of a transistor becomes high relative to the signal ...

AI Technical Summary

Benefits of technology

[0010] There is a need for providing a semiconductor integrated circuit able to reduce the load of the layout design for arranging the power switches and able to reduce the influence of the voltage drop occurring in power switches exerted upon signal delay.

[0016] By setting the drive capability of the switch transistor to a suitable magnitude in accordance with the power consumption of the circuit cell to which power is supplied through the switch transistor, in comparison with the case where the drive capability of the transistor switch is uniformly set, it becomes possible to reduce the circuit area and leakage current while suppressing the reduction of the power supply voltage.

[0017] At least part of each power switch cell may be included in an area under a group of power lines. In this case, the group of branch lines may include a via interconnect line branching from a power line of the group of power lines and extending to the lower layer. Due to this, the density of arrangement of the circuit cells is improved.

[0023] According to one embodiment of the present invention, the degree of freedom of arrangement of the power switch cells becomes high, and automatic design of the layout by the CAD device can be easily realized, so the load of the layout design can be reduced.

[0024] Further, the voltage drop of the power due to the power switch cells can be suppressed, so the influence of the voltage drop occurring in the power switch cells exerted upon the signal delay can be reduced.

Problems solved by technology

For this reason, there are the disadvantages that the load of the design work increases, and the development period of the product becomes long.

Further, along with the reduction of the power supply voltage, a slight voltage drop occurring in a resistive component of the power line starts to exert a large influence upon the delay of the signal.

Namely, the lower the power supply voltage, the smaller the margin of the signal amplitude with respect to the threshold voltage of a transistor, so a large signal delay occurs even if the drop of the power supply voltage is small.

When a transistor switch is arranged in a power line under such a situation, the voltage drop due to this is further added, so the above problem becomes more serious.

Especially, the signal delay at the center of the circuit block where the distance from the external power line becomes long becomes large.

As a result, there is the problem that even if the circuit block normally operates by itself, it no longer operates when a transistor switch is arranged in the external power line.

Further, when the circuit block is further connected to a block of a higher level, there is the problem that the requested timing can no longer be satisfied.

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