Semiconductor integrated circuit

a technology of integrated circuits and semiconductors, applied in the direction of vessel construction, pulse technique, separation process, etc., can solve the problems of small voltage drop occurring in a resistive component of the power line, affecting the delay of the signal, and increasing the load of the design work, so as to reduce the load of layout design, the degree of freedom of arrangement of the power switch cells, and the effect of suppressing the voltage drop of the power due to the power switch cells

a technology of integrated circuits and semiconductors, applied in the direction of vessel construction, pulse technique, separation process, etc., can solve the problems of small voltage drop occurring in a resistive component of the power line, affecting the delay of the signal, and increasing the load of the design work, so as to reduce the load of layout design, the degree of freedom of arrangement of the power switch cells, and the effect of suppressing the voltage drop of the power due to the power switch cells

US20050200383A1Active Publication Date: 2005-09-15SONY CORP
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  • Semiconductor integrated circuit
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  • Semiconductor integrated circuit

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Experimental program
Comparison scheme
Effect test

first embodiment

[0047]FIG. 1 is a view of an example of the configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. In the figure, interconnect lines relating to the power and circuit cells connected to them are schematically illustrated.

[0048] The semiconductor integrated circuit shown in FIG. 1 has a plurality of groups of power lines PL1, a plurality of groups of power lines PL2, a plurality of groups of branch lines BL1 and BL2, a plurality of circuit cells 10, a plurality of power switch cells 20, a circuit block 30, and a plurality of power input cells 41 and 42.

[0049] Note that the groups of power lines PL1 are embodiments of the groups of power lines of the present invention, the groups of branch lines BL2 are embodiments of the groups of branch lines of the present invention, the circuit cells 10 are embodiments of the circuit cells of the present invention, and the power switch cells 20 are embodiments of the power switch cells of th...

second embodiment

[0070] Next, a second embodiment of the present invention will be explained.

[0071] The semiconductor integrated circuit according to the second embodiment shows the configurations of the power switch cells and circuit cells and the structures of the groups of branch lines connecting them in more detail than the semiconductor integrated circuit according to the first embodiment. The overall configuration such as the arrangement of the groups of power lines is the same as that of the semiconductor integrated circuit according to the first embodiment.

[0072]FIG. 4 is a view of an example of the configuration of a circuit cell 11 according to the second embodiment of the present invention. The circuit cell 11 shown in FIG. 4 has an inverter circuit configured as a serial circuit of a p-type MOS transistor Qp1 and an n-type MOS transistor Qn1 and has interconnect lines L111 and L112 supplying power to this inverter circuit. Note that while FIG. 4 shows an inverter circuit cell as one ex...

third embodiment

[0093] Next, a third embodiment of the present invention will be explained.

[0094] The semiconductor integrated circuit according to the third embodiment is obtained by changing parts of the configurations of the power switch cells and the interconnect line structures in the second embodiment explained above. The overall configuration such as the arrangement of the groups of power lines and the configuration of the circuit cells are the same as those of the semiconductor integrated circuits according to the first and second embodiments.

[0095]FIG. 7 is a view of an example of the configuration of a power switch cell 22 according to the third embodiment of the present invention. The power switch cell 22 has an n-type MOS transistor Qn3 and interconnect lines L221 to L223. The n-type MOS transistor Qn3 is an embodiment of the switch circuit of the present invention, the interconnect line L221 is an embodiment of the third interconnect line of the present invention, and the interconnec...

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Abstract

A semiconductor integrated circuit able to reduce a load of layout design when arranging switches in a power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Description

CROSS REFERENCES TO RELATED APPLICATION [0001] The present invention contains subject matter related to Japanese Patent Application JP 2004-067489 filed in the Japanese Patent Office on Mar. 10, 2004, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor integrated circuit, more particularly relates to a semiconductor integrated circuit achieving a reduction of power consumption by using a transistor having a high threshold voltage to cut the supply of power to an unused circuit. [0004] 2. Backgound Art [0005] The power supply voltage of semiconductor integrated circuits have fallen year by year along with the reduction of the power consumption and the miniaturization of processing dimensions. When a signal amplitude becomes small due to the reduction of the power supply voltage, the threshold voltage of a transistor becomes high relative to the signal ...

Claims

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Application Information

Patent Timeline
15 Sep 2005
Publication
US20050200383A1
IPC
H01L23/522; H01L23/528; H01L21/822; H01L27/00; H01L27/02; H01L27/04; H03K19/177
CPC
H01L23/5286; H01L27/0203; H01L27/11807; H03K19/0013; H01L2924/0002; H03K19/0016; H01L2924/00; B63J2/12
Inventors
OGATA, HIROMI