Low-latency start-up for a monolithic clock generator and timing/frequency reference

a clock signal and low-latency startup technology, applied in the direction of oscillation generators, pulse automatic control, resonance circuit tuning, etc., can solve the problems of inability to manufacture as part of the same integrated circuit, affecting the quality reducing the frequency of the clock signal, so as to achieve significant noise reduction, phase noise reduction, and high frequency

Active Publication Date: 2006-01-26
INTEGRATED DEVICE TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011] In addition, the various exemplary embodiments of the invention provide a clock generator and/or a timing and frequency reference having multiple operating modes, including modes such as a power conservation mode, a clock mode, a reference mode, and a pulsed mode. In addition, the various embodiments provide multiple output signals at different frequencies, and provide low-latency and glitch-free switching between these various signals.
[0012] Significantly, the various exemplary embodiments of the invention generate a signif...

Problems solved by technology

The difficulty with such crystal oscillators is that they cannot be fabricated as part of the same integrated circuit (“IC”) that is to be driven by their clock signal.
For example, because such a processor must be connected through outside circuitry (such as on a printed circuit board (PCB)), power dissipation is comparatively increased.
In applications which rely on a finite power supply, such as battery power in mobile communications, such additional power dissipation is detrimental.
In addition, such non-integrated solutions, by requiring an additional IC, increase space and area requirements, whether on the PCB or within the finished product, which is also detrimental in mobile environments.
Moreover, such additional components increase manufacturing and production costs, as an additional IC must be fabr...

Method used

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  • Low-latency start-up for a monolithic clock generator and timing/frequency reference
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  • Low-latency start-up for a monolithic clock generator and timing/frequency reference

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Embodiment Construction

[0080] While the present invention is susceptible of embodiment in many different forms, there are shown in the drawings and will be described herein in detail specific examples and embodiments thereof, with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the specific examples and embodiments illustrated.

[0081] As indicated above, the various embodiments of the invention provide numerous advantages, including the ability to integrate a highly accurate (over PVT and age), low-jitter, free-running and self-referencing clock generator and / or a timing and frequency reference with other circuitry, such as illustrated in FIG. 1. FIG. 1 is a block diagram illustrating an exemplary system embodiment 150 in accordance with the teachings of the present invention. As illustrated in FIG. 1, the system 150 is a single integrated circuit, having a clock generator and / or ti...

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Abstract

An apparatus, system and method are provided for low-latency start-up of a free-running harmonic oscillator. The exemplary apparatus embodiment comprises a first and second current sources to generate first and second currents; a bias current monitor adapted to detect a magnitude of the second current and to provide a control signal when the magnitude of the second current is equal to or greater than a predetermined magnitude; and a bias controller adapted to switch the first current from the oscillator and to switch the second current to the oscillator in response to the control signal. a reference voltage generator, a comparator, and a bias controller. Exemplary embodiments include reference voltage generator, a comparator, and a bias controller.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation-in-part of and claims priority to U.S. patent application Ser. No. 11 / 084,962, filed Mar. 21, 2005, inventors Michael Shannon McCorquodale, Scott Michael Pemia, and Amar Sarbbaseh Basu, entitled “Monolithic Clock Generator and Timing / Frequency Reference” (the “first related application”), which is commonly assigned herewith, the contents of which are incorporated herein by reference, and with priority claimed for all commonly disclosed subject matter, and further claims priority to U.S. Provisional Patent Application Ser. No. 60 / 555,193, filed Mar. 22, 2004, inventor Michael Shannon McCorquodale, entitled “Monolithic and Top-Down Clock Synthesis with Micromachined Radio Frequency Reference” (the “second related application”), which is commonly assigned herewith, the contents of which are incorporated herein by reference, and with priority claimed for all commonly disclosed subject matter. [0002] This a...

Claims

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Application Information

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IPC IPC(8): H03L7/099
CPCH03B5/04H03B5/124H03B2200/0038H03B2200/005H03B2200/0098H03J2200/10H03K23/66H03K23/662H03L1/00H03L1/026H03L3/00H03L7/06H03L7/0812H03L7/099H03L7/18H03L7/24H03B5/1228H03B5/1212H03B5/06
Inventor PERNIA, SCOTT MICHAELMCCORQUODALE, MICHAEL SHANNONKUBBA, SUNDUS
Owner INTEGRATED DEVICE TECH INC
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