Semiconductor memory device and method for manufacturing semiconductor device
a memory device and semiconductor technology, applied in the direction of semiconductor devices, electrical appliances, transistors, etc., can solve the problems of deterioration of the film quality of the lower silicon oxide film, the increase of the demand for miniaturization and high performance of the semiconductor memory, and the multi-layered insulating film. achieve the effect of high reliability and high quality
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Examples
specific embodiments
[0086] Specific embodiments are explained below based on the aforementioned basic structure of the present invention.
first embodiment
[0087] In this embodiment, a semiconductor memory device having an embedded bit line type SONOS structure will be disclosed. A structure of the semiconductor memory device is explained with a method for manufacturing thereof as a matter of convenience.
[0088] This semiconductor memory device is so structured that SONOS transistors in a memory cell region are of a planer type and that CMOS transistors are formed in a peripheral circuit region.
[0089]FIG. 4A to FIG. 13B are schematic cross sectional views showing a method for manufacturing the semiconductor memory device including embedded bit line type SONOS transistors in this embodiment in the order of processes. Here, each A of the drawings shows a memory cell region (a core region), and each B thereof shows a peripheral circuit region. The left side of the A thereof corresponds to a cross section (an X section) taken along the parallel line to a gate electrode (a word line), and the right side corresponds to a cross section (a Y ...
second embodiment
[0122] In this embodiment, a floating gate type semiconductor memory device will be disclosed. A structure of the semiconductor memory device is explained with a method for manufacturing thereof as a matter of convenience.
[0123] The floating gate type transistors are formed in a memory cell region, and CMOS transistors are formed in a peripheral circuit region.
[0124]FIG. 15A to FIG. 26B are schematic cross sectional views showing a method for manufacturing the semiconductor memory device including the floating gate type transistors in this embodiment in the order of processes. It should be noted that, for convenience, the same reference numerals are given to the components or the like explained in the first embodiment. Here, each A of the drawings except FIG. 20 shows a memory cell region (a core region), and each B thereof shows a peripheral circuit region. The left side of the A thereof corresponds to a cross section (an X section) taken along the parallel line to a control gate...
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Abstract
Description
Claims
Application Information
- IPC
- H01L21/31; H01L21/336; H01L21/318; H01L21/8247; H01L27/10; H01L29/788; H01L29/792; H10B20/00; H10B69/00; H10B99/00
- CPC
- H01L21/3145; H01L27/105; Y10S438/954; H01L27/11546; H01L27/11568; H01L27/11526; H01L21/02164; H01L21/022
- Inventors
- NANSEI, HIROYUKI; NAKAMURA, MANABU