Data retention in operational and sleep modes

Abstract

A circuit is disclosed for retaining a signal value during a sleep mode while a portion of said circuit is powered down comprising: a clock signal input operable to receive a clock signal; at least one latch clocked by said clock signal; a data input, a data output and a forward data path therebetween, wherein a signal value is operable to be received at said data input, is clocked through said at least one latch and passes to said data output along said forward data path; at least one of said at least one latch comprises a retention latch operable to retain a signal value during said sleep mode, said retention latch not being located on said forward data path; and a bidirectional tristateable device, said bidirectional tristateable device being arranged between said forward data path and said retention latch and being operable to selectively isolate said retention latch from said forward data path in response to receipt of a first sleep signal; wherein in response to receipt of a second sleep signal, said second sleep signal being received after said first sleep signal, said circuit is operable to enter said sleep mode such that a voltage difference across said portion of said circuit is reduced such that said portion of said circuit is powered down, and a voltage difference across said retention latch and said bidirectional tristateable device is maintained.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to the field of data processing systems. More particularly, this invention relates to circuits and methods of operating circuits that allow for the storage of a signal value in both operational and sleep modes. [0003] 2. Description of the Prior Art [0004] In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency attention is also being turned to reducing static power consumption, i.e. power loss due to leakage currents. One way of addressing this is to provide the circuit with a sleep mode so that it is in effect powered down during these non-operational periods. To reduce static power during these sleep periods, many circuit designs are now making use of on-chip power gating which allows rapid transitions between sleep and funct...

AI Technical Summary

Benefits of technology

[0011] The arrangement of the present invention that provides a data retention device that can retain data in sleep mode and is not itself on the forward data path, is an effective way of retaining data without slowing the critical timing path, which comprises the forward data path. Furthermore, the use of a tristateable device placed between the forward data path and the retention latch which can selectively isolate the retention latch, is a convenient way of retaining data in sleep mode and again does not effect the critical timing path. Removing these devices from the critical timing path allows the designer greater freedom in his selection of components for these devices and therefore allows for the selection of, for example, low leakage components that may not have such high performance.

[0042] As the retention latch and tristateable device are continually powered, it is highly advantageous to make them from low leakage components such as devices having a high threshold voltage. This means that there is very little static power loss from these components. Furthermore, as these components are arranged to be not on the forward data path i.e. not on the critical timing path the provision of low leakage components in this pathway does not affect the performance of the circuit.

Problems solved by technology

To enter a low leakage mode, the power transistors are turned off and the leakage of the design is limited by the leakage of the power transistors.

Although this results in substantial power savings it also results in a loss of state within the targeted circuitry.

A disadvantage of this approach is that the balloon latches consume considerable additional circuit area.

Whilst this approach reduces the increase in circuit overhead associated with providing the data retention capability, it does require control of the three clock signals of the sense amplifier flip-flops or hybrid latch flip-flops with their known disadvantages in terms of speed, power consumption and other factors.

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