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Reliability barrier integration for cu application

a technology of reliability barrier and integration, applied in the direction of superimposed coating process, semiconductor/solid-state device details, coatings, etc., can solve the problems of difficult to provide effective barrier to prevent leakage between lines, and limited high-aspect pvd technology

Inactive Publication Date: 2007-07-05
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach provides a robust barrier layer that prevents copper diffusion while maintaining low resistance and ensuring effective electrical contact, enhancing the integrity and performance of dual damascene structures.

Problems solved by technology

One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials.
However, within the same dielectric layer it is difficult to provide an effective barrier to prevent leakage between lines.
However, common PVD technologies are limited in high aspect structures due to the directional nature of their deposition.
The barrier thickness, and therefore the barrier integrity may be compromised on the sidewall near the structure bottom.
Also, the bottom corners of vias often do not form precise right angles at their intersection.
As a result, it is difficult to deposit a barrier layer that covers these undercuts by PVD because of the limited directionality of deposition by PVD.
Both materials are perceived as being good barriers to Cu diffusion, but are considered unattractive due to their high resistivity.
The highly resistive nature of these materials detrimentally affects the conductivity between the plug and the underlying conductive features, which must be maintained as low as possible to maximize logic device performance.

Method used

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  • Reliability barrier integration for cu application
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  • Reliability barrier integration for cu application

Examples

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example 1

[0041] In one example, a process according to the present invention was performed on a substrate having a 0.25 μm via with about a 4:1 aspect ratio and a trench. The patterned substrate was first introduced into a CVD chamber, such as a TxZ® chamber, commercially available from Applied Materials, Inc., Santa Clara, Calif., where about 50 Å to about 100 Å of SixNy was deposited on the substrate using CVD techniques. The substrate was then moved into a Pre-clean II chamber (available from Applied Materials, Inc., located in Santa Clara, Calif.), where the substrate was subjected to an argon / hydrogen etching environment for about 20 seconds. RF / DC powers of about 300 / 300 W were used. Next, the substrate was moved into a PVD chamber where about 400 Å of TaN was deposited on the substrate in the field. Next, the substrate was introduced into a CVD chamber where about 400 Å of CVD Cu was deposited on the substrate as a wetting layer. Then, Cu was sputtered onto the substrate to complete t...

example 2

[0042] In another example, a patterned substrate with a dual damascene trench structure and a via opened to an underlying Cu wiring was first introduced into a multichamber processing apparatus having a sputter clean chamber, a CVD barrier chamber, a PVD barrier chamber, and a PVD Cu chamber. 50 Å of TiSixN was deposited on the substrate in a CVD barrier chamber at a pressure of less than 10 Torr and at a temperature of about 300° C. to about 380° C. by reacting TDMAT in a N2 / H2 environment to form a plasma. The substrate was then treated with a SiH4 soak. The deposited TiSixN conformally covered both the via and trench structure. In the next step, the substrate was moved to the sputter clean chamber, and subjected to argon / hydrogen etch to etch off the TiSixN film deposited at the bottom of the via. The etching was continued past the bottom of the via into the underlying Cu wiring to remove about 5 to 10 Å of the underlying Cu wiring. The etch process also removed the TiSixN film a...

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Abstract

Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of co-pending U.S. patent application Ser. No. 10 / 841,086, filed May 7, 2004, which is a continuation of U.S. patent application Ser. No. 10 / 052,681, filed Jan. 17, 2002, now issued as U.S. Pat. No. 7,026,238, which is a continuation-in-part of U.S. patent application Ser. No. 08 / 856,116, filed May 14, 1997, which is hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] Embodiments of the invention relate to a deposition sequence and related hardware for manufacturing a plug and line typical of a dual damascene structure utilizing a thin conformal barrier layer formed on the walls of the feature. [0004] 2. Description of the Related Art [0005] Modern semiconductor integrated circuits usually involve multiple conductive layers separated by dielectric (insulating) layers, such as oxide layers. The conductive layers are electrically interconnected by holes pe...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C23C28/00C23C28/02H01L21/285H01L21/768
CPCC25D5/02H01L21/2855H01L21/28556H01L21/28562H01L21/76804H01L23/53238H01L21/76843H01L21/76844H01L21/76846H01L21/76877H01L23/5226H01L21/76831H01L2924/0002H01L2924/00
Inventor XI, MINGSMITH, PAUL FREDERICKCHEN, LINGYANG, MICHAEL X.CHANG, MEICHEN, FUSENMARCADAL, CHRISTOPHELIN, JENNY C.
Owner APPLIED MATERIALS INC