P-channel non-volatile memory and operating method thereof

Inactive Publication Date: 2007-08-09
EMEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0008] Accordingly, at least one objective of the present invention is to provide a P-channel non-volatile memory and operating met

Problems solved by technology

Moreover, the access speed is fast, the storage capacity per unit weight is large and the access device occupies only a small volume.
The N-channel non-volatile memory has small channel current and poor energy utilization.
Therefore, in a low energy consumption portable electronic

Method used

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  • P-channel non-volatile memory and operating method thereof
  • P-channel non-volatile memory and operating method thereof
  • P-channel non-volatile memory and operating method thereof

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Example

[0035] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0036]FIG. 1 is a schematic cross-sectional view of a P-channel non-volatile memory according to one embodiment of the present invention. As shown in FIG. 1, the P-channel non-volatile memory includes a substrate 100, a well 101, a first memory cell 103 and a second memory cell 105, for example. The substrate 100 is a P-type substrate, for example. The well 101 is an N-well disposed in the substrate, for example. The first memory cell 103 and the second memory cell 105 are disposed over the well 101 and are serially connected together, for example.

[0037] The first memory cell 103 includes a tunneling dielectric layer 110a, a charge storage structure 110b, a barrier dielectric layer 110c, a gate 12...

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Abstract

A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a memory and operating method thereof. More particularly, the present invention relates to a P-channel non-volatile memory and operating method thereof. [0003] 2. Description of the Related Art [0004] Electrically erasable programmable read-only-memory (EEPROM) is a type of non-volatile memory that allows multiple data entry, reading and erasing operations. The stored data will be retained even after power to the device is removed. Moreover, the access speed is fast, the storage capacity per unit weight is large and the access device occupies only a small volume. With these advantages, EEPROM has become one of the most widely adopted non-volatile memories for personal computer and electronic equipment. [0005] A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. To prevent a conventional EEPROM from over-erasing in an erasing operation and leadin...

Claims

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Application Information

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IPC IPC(8): H01L29/788
CPCH01L27/115H10B69/00
Inventor LIN, YEN-TAI
Owner EMEMORY TECH INC
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