Phase alignment mechanism for minimizing the impact of integer-channel interference in a phase locked loop

a phase locking loop and integer channel technology, applied in the field of data communication, can solve the problems of not being able to tolerate output of pll, and achieve the effect of minimizing the impact of interferen

Inactive Publication Date: 2008-08-14
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0037]There is thus provided in accordance with the invention, a method of minimizing the impact of interference to a frequency reference from a radio frequency (RF) signal, the method comprising steps of determining a desired phase relationship between the frequency reference input and the RF signal and adjusting the phase of the RF signal in accordance with the desired phase relationship.
[0038]There is also provided in accordance with the invention, a phase locked loop (PLL) comprising a frequency reference input for receiving a reference clock, a controllable oscillator for generating a radio frequency (RF) clock, a phase detector operational on the reference clock, the phase detector generating phase error samples in accordance therewith and a phase adjustor coupled to the controllable oscillator and the phase detector, the phase adjustor operative to receive the phase error samples and adjust the phase of t...

Problems solved by technology

The impact of such interference on the output of the PLL may manifest itself in the form of excessive phase error or distortion, which a receiver based on it would often not tolerate due to degradation in reception quality that this could result in, and which a transmitter would not tolerate due to the possible violation of the transmitter's spectral mask an...

Method used

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Notation Used Throughout

[0060]The following notation is used throughout this document.

TermDefinitionACAlternating CurrentACWAmplitude Control WordADCAnalog to Digital ConverterADPLLAll Digital Phase Locked LoopAMAmplitude ModulationASICApplication Specific Integrated CircuitAVIAudio Video InterfaceBISTBuilt-In Self TestBMPWindows BitmapCMOSComplementary Metal Oxide SemiconductorCPUCentral Processing UnitDBBDigital BasebandDCDirect CurrentDCODigitally Controlled OscillatorDCXODigitally Controlled Crystal OscillatorDPADigitally Controlled Power AmplifierDRACDigital to RF Amplitude ConversionDRPDigital RF Processor or Digital Radio ProcessorDSLDigital Subscriber LineDSPDigital Signal ProcessorEDGEEnhanced Data Rates for GSM EvolutionEDREnhanced Data RateEPROMErasable Programmable Read Only MemoryFCWFrequency Command WordFIBFocused Ion BeamFMFrequency ModulationFPGAField Programmable Gate ArrayGMSKGaussian Minimum Shift KeyingGPSGlobal Positioning SystemGSMGlobal System for Mobile commu...

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Abstract

A novel and useful apparatus for and method of minimizing the impact of interference on the phase error performance in a phase locked loop (PLL) at integer channels by adjustment of the phase of the interfering signal such that its impact on the reference signal is minimized. Phase control is achieved by use of the digital architecture of the ADPLL and its insensitivity to an arbitrary phase bias introduced between its digitally represented output and reference phase signals. The optimal phase relationship for each integer channel is determined through a calibration procedure in which the phase is swept and the optimal phase is recorded. Before the transmission of a payload on an integer channel, the phase relationship between the output RF signal and the input reference signal is adjusted to the value found to be optimal for that frequency, based on the values previously recorded during the calibration procedure.

Description

REFERENCE TO PRIORITY APPLICATION[0001]This application claims priority to U.S. Provisional Application Ser. No. 60 / 889,334, filed Feb. 12, 2007, entitled “Dithering of Frequency Reference Through Bond Wires”, incorporated herein by reference in its entirety.FIELD OF THE INVENTION[0002]The present invention relates to the field of data communications and more particularly relates to an apparatus for and method of phase alignment for minimizing the impact of integer-channel interference in a phase locked loop (PLL).BACKGROUND OF THE INVENTION[0003]A current trend in modern radio design is the attempt to continually increase the level of integration. The integration of wireless transceivers within digital Systems on Chips (SoCs), driven by cost reduction demands and the advances in technology, creates various challenges related with the coexistence of the various functions within the SoC. The many analog and digital functions, which operate in proximity and share the same die, potenti...

Claims

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Application Information

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IPC IPC(8): H04L7/00
CPCH03L2207/50H03L7/1806
Inventor ELIEZER, OREN E.ENTEZARI, MANOUCHEHRSTASZEWSKI, ROBERT B.BHATARA, SUMEER
Owner TEXAS INSTR INC
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