Fabrication of RRAM Cell Using CMOS Compatible Processes

Abstract

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

Description

BACKGROUND[0001]1. Field of the Disclosure[0002]Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to the fabrication of an RRAM cell with, in one embodiment, one or more bottom electrodes formed by silicidation using CMOS compatible processes.[0003]2. Description of the Related Art[0004]Memory circuits and devices are widely used in the electronics industry. In general, memory devices permit the storage of a “bit” of information, i.e., a “1” (logically high) or a “0” (logically low) signal. Vast numbers of these memory devices are formed on a single chip so as to permit the storage of a vast quantity of digital information. Various forms of such devices, and read / write circuitry employed with such devices, have been used in the industry for years, e.g., RAM (Random Access Memory) devices, ROM (Read Only Memory) devices, EEPROM (Electrically Erasable Read Only Memory) devices, etc.[0005]Nonvolatile memory is a type of memory that ...

AI Technical Summary

Benefits of technology

[0010]The following presents a simplified summary of the present disclosure in order to provide a basic understanding of some aspects disclosed herein. This summary is not an exhaustive overview of the disclosure, nor is it intended to identify key or critical elements of the subject matter disclosed here. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

[0011]Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. In the disclosed examples, the RRAM devices disclosed herein may be of a single bit or a dual bit configuration. In one illustrative embodiment, a resistance random access memory device is disclosed which includes a semiconducting substrate, a metal silicide top electrode positioned above the substrate, a single metal silicide bottom electrode formed at least partially in said substrate, wherein at least a portion of the single bottom electrode is positioned below an entire width of the top electrode and at least one insulating layer positioned between the top electrode and single bottom electrode. In another illustrative example, a resistance random access memory device includes a semiconducti

Problems solved by technology

Such a layered construction of the prior art RRAM device 100 makes it more difficult to incorporate it into integrated circuit devices that are manufactured using modern CMOS processing technology and methods.

Such height differences can lead to patterning errors in photolithography operations and / or mandate additional processing steps be taken to avoid or reduce the adverse effects of such height differences, e.g., the performance of one or more additional deposition and planarization processes.

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