Method and apparatus for aligning a clock signal and a data strobe signal in a memory system

Abstract

A method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory, and a corresponding memory system are provided. The method comprising the steps of: putting the memory into a write levelling mode; incrementing an alignment delay applied to the data strobe signal until a transition point occurs at which a response of the memory to issuance of the data strobe signal transitions to an inverse state; performing an oversampling of the response of the memory over a selected interval following said transition point; repeating the steps of incrementing and performing an oversampling until, for a selected alignment delay, a majority of results of the oversampling is in the inverse state; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of the clock signal, the identified clock cycle responsible for the transition point; and applying the selected alignment delay to the data strobe signal and applying a clock cycle selection to a data path in the system to match the identified clock cycle.

Description

BACKGROUND OF THE INVENTION[0001]This application incorporates by reference the subject matter disclosed in each of the concurrently filed applications entitled “An Interface For Controlling The Phase Alignment Of Clock Signals For A Recipient Device” by Gyan Prakash et al (attorney reference no. 550-1573) and “A data signal receiver and method of calibrating a data signal receiver” by Nidhar Kumar et al (attorney reference no. 550-1572).”[0002]1. Field of the Invention[0003]The present invention relates to a method and apparatus for aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory. More particularly, this invention relates to determining a delay applied to the data strobe signal to align it with the clock signal.[0004]2. Description of the Prior Art[0005]In a memory system comprising a memory controller and a memory, it is known for the memory controller to carry out a write levelling calibration of the memory system during an...

AI Technical Summary

Benefits of technology

This patent is about an improved way to align data with a clock signal in a memory system. It uses a technique called oversampling to identify the alignment between the two signals. Another advantage is that it allows the alignment to be performed across multiple clock cycles without adding extra delay or jitter to the system. The process involves adding a partial clock cycle to the alignment delay and then iteratively masking clock cycles to ensure the data strobe signal doesn't interfere with the setup / hold time. Overall, this patent provides a more accurate and efficient way to align data with a clock signal in a memory system.

Problems solved by technology

As contemporary memory systems, in particular dual data rate systems, progress to ever higher clock rates and data transfer rates, the challenges presented in carrying out this write levelling process are growing.

However, this mechanism has now been found not to be practical in contemporary systems (in particular at the above mentioned high data rates) where system jitter and write levelling uncertainty (tWLH, tWLH) are present.

However, increasing the length of the DRAM clock path, whilst on the one hand allowing it to provide the required degree of write levelling, on the other hand also makes it more susceptible to power supply noise induced jitter, unless built using current mode logic (CML) which typically has undesirably high power requirements and further requires custom implementation.

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