System and method for fabricating high voltage power mosfet

Abstract

A high voltage power MOSFET includes a semiconductor substrate doped by a first conducting type, a source doped by a second conducting type and over the semiconductor substrate, and a drain region doped by the second conducting type and on the semiconductor substrate. One or more drain layers doped by the second conducting type and on the semiconductor substrate span between the body region and the drain region. An insulating layer is formed on at least a portion of the body region and over the one or more drain layers. A voltage regulating layer on the insulating layer can produce voltage distributions in the one or more drain layers to deplete charge carriers to increase blockage voltage in an off state, and to accumulate charge carriers in an on state to reduce on-state resistance.

Description

BACKGROUND OF THE INVENTION[0001]This application relates to semiconductor devices, and more particularly, to high voltage power metal-oxide-semiconductor field-effect transistors (MOSFET).[0002]One of the most important components in a high voltage semiconductor power MOSFET is the lightly doped drain (LDD) region (also known as “drift” region). While LDD helps a device supporting high applied voltage during the voltage blocking “off” state, it also heavily limits the current conductivity during “on” state then current is conducting. In a conventional high voltage power MOSFET, due to the LDD resistance, the total on-resistance (Ron) rapidly increases with the desired reverse breakdown voltage (Vb). The relationship can be roughly expressed as a function of Ron˜Vb3. For example, in a 750V conventional vertical MOSFET, the LDD contributes almost 99% of the device's total on-resistance.[0003]There have been a few methods developed over the years to reduce the on-resistance. They help...

AI Technical Summary

Benefits of technology

This patent is about increasing the ability of high voltage semiconductor power MOSFET devices to handle high voltages. The invention achieves this by embedding an electrical field in the device's LDD region, which maintains high conductivity. The control mechanism driving the embedded structures allows the LDD to be driven into accumulation, reducing on-resistance. The conducting path, separated from the LDD region by a thin layer of insulating dielectric material, provides a stable embedded electrical field depleting charge carriers during the voltage blocking period, enhancing the blocking voltage. The conductivity of the device can be further increased by biasing LDD into accumulation during on-state. The invention also allows for three-dimensional embodiments, where depletion is enhanced by reducing the distance between adjacent conducting paths. With advancements in semiconductor technology, the device's dimensions can be reduced and conductivity increased.

Problems solved by technology

Some disclosed devices have the path controlled by MOSFET gate and can be biased in accumulation in conduction mode, which results in significant on-resistance reduction.

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