Semiconductor device and manufacturing method thereof

Abstract

A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input / output (I / O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I / O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device including a core region and an input / output region and a manufacturing method thereof.2. Description of the Prior Art[0002]In the continuously improved semiconductor integrated circuit technology, the sizes of the semiconductor devices become smaller for increasing the integrity of the integrated circuit. In the scaling down process, the thickness control of layers in the semiconductor device becomes more and more critical. For improving the metal-oxide-semiconductor field effect transistor (MOSFET) device performance as feature sizes continue to decrease, the traditional gate oxide and polysilicon gate electrode are replaced by a high dielectric constant (high-k) gate dielectric and a metal gate electrode. In high-k gate stacks, the interfacial layer (IL) underlying the high-k dielectri...

AI Technical Summary

Benefits of technology

This approach improves manufacturing yield and electrical performance by maintaining the oxide dielectric layer integrity and controlling gate structure dimensions effectively, while allowing for different voltage operations on the same die.

Problems solved by technology

However, the manufacturing process may become complicated and / or negative effects may be generated by the approaches of forming gate dielectric layers with different thicknesses, and the manufacturing yield may be influenced accordingly.

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