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Wafer-bonding structure and method of forming thereof

Inactive Publication Date: 2021-09-23
INTEGRATED SILICON SOLUTION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present patent describes a method for bonding wafers together using a through silicon via (TSV) structure and a conductive filler. The TSV structure is formed on one side of a seal ring structure on one of the wafers, and the seal ring structure is connected to the other side of the bonding surface on the same wafer and a portion of the seal ring structure on another wafer. A bonding pad is formed on the outer surface of the wafer with the TSV structure. This method provides a reliable and efficient way to bond wafers together. The resulting wafer-bonding structure has a high bonding strength and is useful in various applications.

Problems solved by technology

Also, an edge chipping and a moisture penetration are easily happened during sawing the wafer-bonding structure.

Method used

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  • Wafer-bonding structure and method of forming thereof
  • Wafer-bonding structure and method of forming thereof
  • Wafer-bonding structure and method of forming thereof

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Embodiment Construction

[0012]FIG. 1 is a step flow chart of a method of forming a wafer-bonding structure 100 according to an embodiment of the present disclosure. In FIG. 1, the method of forming the wafer-bonding structure 100 includes a surface treatment step S101, a wafer-bonding step S102, a through silicon via (TSV) forming step S103 and a forming bonding pad step S104.

[0013]FIG. 2 is a schematic view of the surface treatment step S101 according to the embodiment of FIG. 1. In FIGS. 1 and 2, a bonding surface of each of at least two wafers is performed a surface treatment before the wafer-bonding step S102. According to the embodiment of FIG. 1, a number of the wafers is two, but is not limited thereto. Further, the wafer 21 has the bonding surface 21a, and the wafer 22 has the bonding surface 22a. In detail, the surface treatment step S101 is to densify a silicon oxide (not shown) on the bonding surfaces 21a, 22a to avoid voids formed by the bonding surfaces 21a, 22a. Also, a roughness of the bondi...

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Abstract

A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.

Description

BACKGROUNDTechnical Field[0001]The present disclosure relates to a wafer-bonding structure and a method of forming thereof.Description of Related Art[0002]Nowadays, a wafer-bonding structure is well established technology for a wafer-level packaging. In a significant effort is focused on a wafer-level three-dimensional integration as a viable solution for increasing functionality and overcoming a bottleneck of a wire-bonding process.[0003]However, an oxide is easily formed on a bonding surface of a wafer to increase a resistance of the wafer-bonding structure. Also, an edge chipping and a moisture penetration are easily happened during sawing the wafer-bonding structure. Hence, decreasing an effect of the oxide formed on the bonding surface and avoiding the edge chipping and the moisture penetration as possible are important for the wafer-bonding structure.SUMMARY[0004]According to one aspect of the present disclosure, a method of forming a wafer-bonding structure includes a wafer-b...

Claims

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Application Information

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IPC IPC(8): H01L23/00H01L21/768H01L23/48
CPCH01L24/80H01L24/03H01L21/76877H01L21/76898H01L23/481H01L2224/05147H01L2224/80095H01L2224/80009H01L2224/05624H01L2224/05009H01L24/05H01L2224/08145H01L23/585H01L2224/80097H01L2224/80013H01L2224/80055H01L2224/80075H01L2224/04042H01L2224/0557H01L2224/05568H01L24/94H01L24/92H01L25/0657H01L2225/06541H01L2224/80895H01L2224/80896H01L2224/94H01L2224/80357H01L2224/80001
Inventor WANG, HSINGYA ARTHURCHOU, SHENG-YUANWANG, YU-TINGCHANG, WAN-YI
Owner INTEGRATED SILICON SOLUTION
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