High density cantilevered probe for electronic devices

a cantilevered probe, high density technology, applied in the direction of printed circuit manufacturing, printed element electric connection formation, instruments, etc., can solve the problems of limiting the substrate made from a silicon wafer or other semiconductor material, rigid and not providing a wiping interface with the mating contact, and the substrate used for fabrication of this probe fixture is limited to semiconductor wafers which are relatively expensive. , to achieve the effect of reducing the potential for damaging the interconnect circuit wiring and high density probe structur

Inactive Publication Date: 2001-12-11
TOKYO ELECTRON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

Yet another object of the present invention is to provide a fabrication process that minimizes the potential for damaging the interconnect circuit wiring in the substra

Problems solved by technology

Although this technique is similar to the probe structure described in this patent application, it is limited to substrates made from a silicon wafer or other semiconductor materials.
The probes described in this patent are rigid and do not provide a wiping interface with the mating contacts on the IC device.
Also, the substrate used for fabrication of t

Method used

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  • High density cantilevered probe for electronic devices
  • High density cantilevered probe for electronic devices
  • High density cantilevered probe for electronic devices

Examples

Experimental program
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Embodiment Construction

FIG. 1 shows a cross section of a test substrate (10) and high density cantilever test probe (20) according to the present invention. The test substrate (10) provides a rigid base for attachment of the probe structures (20) and fan out wiring from the high density array of probe contacts to a larger grid of pins or other interconnection means to the equipment used to electrically test the integrated circuit device. The fan out substrate can be made from various materials and constructions including single and multi-layer ceramic with thick or thin wiring, silicon wafer with thin film wiring, or epoxy glass laminate construction with high density copper wiring. The cantilever test probes (20) are attached to the first surface (11) of the substrate (10). The probes are used to contact the bond pads (31) on the integrated circuit device (30). The surface of the bond pads (31) are recessed slightly below the surface of the passivation layer (32) on the integrated circuit device (30).

The...

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Abstract

Connectors for electronic devices are described. The connector is formed by ball bonding a plurality of wires to contact locations on a fan out substrate surface. The wires are cut off leaving stubs. A patterned polymer sheet having electrical conductor patterns therein is disposed over the stubs which extend through holes in the sheet. The ends of the wires are flattened to remit the polymer sheet in place. The wire is connected to an electrical conductor on the polymer sheet which is converted to a contact pad on the polymer sheet. A second wire is ball bonded to the pad on the polymer sheet and cut to leave a second stub. The polymer sheet is laser cut so that each second stub is free to move independently of the other second studs. The ends of the second stubs are disposed against contact locations of an electronic device, such as an FC chip, to test the electronic device.

Description

The present invention is directed to probe structures for testing of electrical interconnections to integrated circuit devices and other electronic components and particularly to testing integrated circuit devices with flat or recessed surfaces for wired bonded interconnections.Integrated circuit (IC) devices and other electronic components are normally tested to verify the electrical function of the device and certain devices require high temperature burn-in testing to accelerate early life failures of these devices. The various types of interconnection methods used to test these devices include permanent, semi-permanent, and temporary attachment techniques. The permanent and semi-permanent techniques that are typically used include soldering and wire bonding to provide a connection from the IC device to a substrate with fan out wiring or a metal lead frame package. The temporary attachment techniques include rigid and flexible probes that are used to connect IC device to a substra...

Claims

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Application Information

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IPC IPC(8): G01R1/067G01R1/073G01R3/00H05K3/32H05K3/40
CPCG01R1/06727G01R1/06744G01R1/07342G01R3/00H05K3/326H05K3/4015
Inventor BEAMAN, BRIAN SAMUELFOGEL, KEITH EDWARDLAURO, PAUL ALFREDNORCOTT, MAURICE HEATHCOTESHIH, DA-YUAN
Owner TOKYO ELECTRON LTD
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