I-shaped and L-shaped contact structures and their fabrication methods

Abstract

Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]This invention relates generally to semiconductor devices and fabrication methods and, more particularly, to methods for fabricating contacts for use in phase change memory devices.[0003]2. Description of Related Art[0004]Solid-state memory devices are used throughout the field of electronics. Typical memory applications include dynamic random access memory (DRAM), static random access memory (SRAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash memory. These can be divided into volatile and non-volatile memories. The primary element of the non-volatile devices, such as an EEPROM, typically employs a floating gate field effect transistor. A charge is stored on the gate of the field effect transistor to program each memory bit and has limited reprogrammability. These classes of memories may also be relatively slow to program...

AI Technical Summary

Benefits of technology

[0012]The present invention has, for example, further application is semiconductor devices generally as it affords a means of fabricating ultra-small contacts thereby permitting further reduction in the sizes of semiconductor devices. Additionally, with fabrication methods of the present invention, each contact region is on only one side of the support structure (defined below), enabling better design rules and a wider process window, with no wasted structure. In illustrated embodiments, the memory material may comprise a phase-change material such as chalcogenide.

[0013]The method of the present invention employs deposition and etch processes known in the art of semiconductor processing which may be readily applied to produce relatively uniform results. The methods may also result in top electrodes that are self-aligned to the contact structures, forming self-aligned I-shaped or L-shaped contact structure arrays. This characteristic may additionally permit photo process windows to be enlarged. Additionally, the pitch of the support structure is twice that of the bit line, resulting in a pitch that is not very small, thus facilitating relative ease in control of the support structure etch process.

Problems solved by technology

A charge is stored on the gate of the field effect transistor to program each memory bit and has limited reprogrammability.

These classes of memories may also be relatively slow to program.

Although the memory cells of SRAMs, ROMs, EPROMs, EEPROMs, and flash memories do not require refreshing, they may suffer from disadvantages such as lower storage densities, larger size, and greater cost to manufacture compared to volatile DRAM devices.

One characteristic common among solid state memory devices including phase change memory devices is significant power consumption, particularly in setting or resetting memory elements.

Even as downscaling of component sizes continues, power consumption continues to be a significant consideration, particularly in portable devices that rely on power cells (e.g., batteries).

With conventional semiconductor processing technology, the minimum achievable dimensions of a contact for a chalcogenide memory device may be limited by photolithography tools.

Such dimensions may cause switching currents, voltages, and switching times to be too large and cycle life to be too small for integration with many leading-edge semiconductor technologies.

Additionally, conventional chalcogenide memory fabrication methods may not be able to efficiently and reliably produce the uniform memory elements needed for large-scale memory devices.

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